Merging r238146:
------------------------------------------------------------------------
r238146 | thomas.stellard | 2015-05-25 12:15:50 -0400 (Mon, 25 May 2015) | 6 lines
R600/SI: Use NAME rather than opName as the key to the MCOpcode tables
This lets us drop a parameter the opName parameter to the VINTRP
multiclass and makes it possible to create multiple VINTRP defs
with the same asm mnemonic.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@240284 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
index a749e7f..85b859e 100644
--- a/lib/Target/R600/SIInstrInfo.td
+++ b/lib/Target/R600/SIInstrInfo.td
@@ -1421,16 +1421,16 @@
VINTRPe_vi <op>,
SIMCInstr<opName, SISubtarget.VI>;
-multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
+multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
string disableEncoding = "", string constraints = "",
list<dag> pattern = []> {
let DisableEncoding = disableEncoding,
Constraints = constraints in {
- def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
+ def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
- def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
+ def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
- def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
+ def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
}
}
diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
index 05df654..af25614 100644
--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
@@ -1377,14 +1377,14 @@
// FIXME: Specify SchedRW for VINTRP insturctions.
defm V_INTERP_P1_F32 : VINTRP_m <
- 0x00000000, "v_interp_p1_f32",
+ 0x00000000,
(outs VGPR_32:$dst),
(ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
"v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [$m0]",
"$m0">;
defm V_INTERP_P2_F32 : VINTRP_m <
- 0x00000001, "v_interp_p2_f32",
+ 0x00000001,
(outs VGPR_32:$dst),
(ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
"v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]",
@@ -1392,7 +1392,7 @@
"$src0 = $dst">;
defm V_INTERP_MOV_F32 : VINTRP_m <
- 0x00000002, "v_interp_mov_f32",
+ 0x00000002,
(outs VGPR_32:$dst),
(ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
"v_interp_mov_f32 $dst, $src0, $attr_chan, $attr, [$m0]",