commit 3665fd9f2bfce2c18982c0b61487804325f09cae
author Tom Stellard <thomas.stellard@amd.com> Mon Jun 22 14:58:16 2015 +0000
committer Tom Stellard <thomas.stellard@amd.com> Mon Jun 22 14:58:16 2015 +0000
tree a73732b278479f28b6d259411150ab811468f36e
parent b3dd66a5589f41754ab9614a5e7cc283213f0222

Merging r237164:

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r237164 | thomas.stellard | 2015-05-12 14:59:17 -0400 (Tue, 12 May 2015) | 10 lines

R600/SI: Fix bug in VGPR spilling

AMDGPU::SI_SPILL_V96_RESTORE was missing from a switch statement, which
caused the srsrc and soffset register to not be set correctly.

This commit replaces the switch statement with a SITargetInfo query
to make sure all spill instructions are covered.

Differential Revision: http://reviews.llvm.org/D9582

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@240283 91177308-0d34-0410-b5e6-96231b3b80d8