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Zi Xuan Wucb380722021-11-18 10:22:21 +08001//===-------- CompressInstEmitter.cpp - Generator for Compression ---------===//
Sameer AbuAsalb881dd72018-04-06 21:07:05 +00002//
Chandler Carruthca6d7192019-01-19 08:50:56 +00003// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Sameer AbuAsalb881dd72018-04-06 21:07:05 +00006//
Zi Xuan Wucb380722021-11-18 10:22:21 +08007// CompressInstEmitter implements a tablegen-driven CompressPat based
8// Instruction Compression mechanism.
Sameer AbuAsalb881dd72018-04-06 21:07:05 +00009//
Zi Xuan Wucb380722021-11-18 10:22:21 +080010//===----------------------------------------------------------------------===//
Sameer AbuAsalb881dd72018-04-06 21:07:05 +000011//
Zi Xuan Wucb380722021-11-18 10:22:21 +080012// CompressInstEmitter implements a tablegen-driven CompressPat Instruction
13// Compression mechanism for generating compressed instructions from the
14// expanded instruction form.
Sameer AbuAsalb881dd72018-04-06 21:07:05 +000015
16// This tablegen backend processes CompressPat declarations in a
17// td file and generates all the required checks to validate the pattern
18// declarations; validate the input and output operands to generate the correct
19// compressed instructions. The checks include validating different types of
20// operands; register operands, immediate operands, fixed register and fixed
21// immediate inputs.
22//
23// Example:
Zi Xuan Wucb380722021-11-18 10:22:21 +080024// /// Defines a Pat match between compressed and uncompressed instruction.
25// /// The relationship and helper function generation are handled by
26// /// CompressInstEmitter backend.
27// class CompressPat<dag input, dag output, list<Predicate> predicates = []> {
28// /// Uncompressed instruction description.
Sameer AbuAsalb881dd72018-04-06 21:07:05 +000029// dag Input = input;
Zi Xuan Wucb380722021-11-18 10:22:21 +080030// /// Compressed instruction description.
31// dag Output = output;
32// /// Predicates that must be true for this to match.
33// list<Predicate> Predicates = predicates;
34// /// Duplicate match when tied operand is just different.
35// bit isCompressOnly = false;
Sameer AbuAsalb881dd72018-04-06 21:07:05 +000036// }
37//
38// let Predicates = [HasStdExtC] in {
39// def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
40// (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
41// }
42//
Zi Xuan Wucb380722021-11-18 10:22:21 +080043// The <TargetName>GenCompressInstEmitter.inc is an auto-generated header
44// file which exports two functions for compressing/uncompressing MCInst
45// instructions, plus some helper functions:
Sameer AbuAsalb881dd72018-04-06 21:07:05 +000046//
Jay Foad94474cd2020-11-06 14:19:59 +000047// bool compressInst(MCInst &OutInst, const MCInst &MI,
Craig Topper53801ff2023-01-17 11:50:54 -080048// const MCSubtargetInfo &STI);
Sameer AbuAsalb881dd72018-04-06 21:07:05 +000049//
Jay Foad94474cd2020-11-06 14:19:59 +000050// bool uncompressInst(MCInst &OutInst, const MCInst &MI,
Sameer AbuAsalb881dd72018-04-06 21:07:05 +000051// const MCSubtargetInfo &STI);
52//
Ana Pazosead53f62019-12-16 15:09:48 -080053// In addition, it exports a function for checking whether
54// an instruction is compressable:
55//
56// bool isCompressibleInst(const MachineInstr& MI,
Craig Topper47afb8f2023-01-17 18:04:55 -080057// const <TargetName>Subtarget &STI);
Ana Pazosead53f62019-12-16 15:09:48 -080058//
Sameer AbuAsalb881dd72018-04-06 21:07:05 +000059// The clients that include this auto-generated header file and
60// invoke these functions can compress an instruction before emitting
61// it in the target-specific ASM or ELF streamer or can uncompress
62// an instruction before printing it when the expanded instruction
63// format aliases is favored.
64
65//===----------------------------------------------------------------------===//
66
67#include "CodeGenInstruction.h"
NAKAMURA Takumi90f0cbe2023-02-17 00:28:07 +090068#include "CodeGenRegisters.h"
Sameer AbuAsalb881dd72018-04-06 21:07:05 +000069#include "CodeGenTarget.h"
70#include "llvm/ADT/IndexedMap.h"
71#include "llvm/ADT/SmallVector.h"
Sameer AbuAsalb881dd72018-04-06 21:07:05 +000072#include "llvm/ADT/StringMap.h"
73#include "llvm/Support/Debug.h"
74#include "llvm/Support/ErrorHandling.h"
75#include "llvm/TableGen/Error.h"
76#include "llvm/TableGen/Record.h"
77#include "llvm/TableGen/TableGenBackend.h"
Sameer AbuAsalbbf18112019-06-10 17:15:45 +000078#include <set>
Sameer AbuAsalb881dd72018-04-06 21:07:05 +000079#include <vector>
80using namespace llvm;
81
82#define DEBUG_TYPE "compress-inst-emitter"
83
84namespace {
Zi Xuan Wucb380722021-11-18 10:22:21 +080085class CompressInstEmitter {
Sameer AbuAsalb881dd72018-04-06 21:07:05 +000086 struct OpData {
87 enum MapKind { Operand, Imm, Reg };
88 MapKind Kind;
89 union {
Zi Xuan Wucb380722021-11-18 10:22:21 +080090 // Operand number mapped to.
91 unsigned Operand;
92 // Integer immediate value.
93 int64_t Imm;
94 // Physical register.
95 Record *Reg;
Sameer AbuAsalb881dd72018-04-06 21:07:05 +000096 } Data;
Zi Xuan Wucb380722021-11-18 10:22:21 +080097 // Tied operand index within the instruction.
98 int TiedOpIdx = -1;
Sameer AbuAsalb881dd72018-04-06 21:07:05 +000099 };
100 struct CompressPat {
Zi Xuan Wucb380722021-11-18 10:22:21 +0800101 // The source instruction definition.
102 CodeGenInstruction Source;
103 // The destination instruction to transform to.
104 CodeGenInstruction Dest;
105 // Required target features to enable pattern.
106 std::vector<Record *> PatReqFeatures;
107 // Maps operands in the Source Instruction to
108 IndexedMap<OpData> SourceOperandMap;
109 // the corresponding Dest instruction operand.
110 // Maps operands in the Dest Instruction
111 // to the corresponding Source instruction operand.
112 IndexedMap<OpData> DestOperandMap;
113
Craig Topper0d57e1d2021-01-20 09:19:57 -0800114 bool IsCompressOnly;
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000115 CompressPat(CodeGenInstruction &S, CodeGenInstruction &D,
116 std::vector<Record *> RF, IndexedMap<OpData> &SourceMap,
Craig Topper0d57e1d2021-01-20 09:19:57 -0800117 IndexedMap<OpData> &DestMap, bool IsCompressOnly)
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000118 : Source(S), Dest(D), PatReqFeatures(RF), SourceOperandMap(SourceMap),
Craig Topper0d57e1d2021-01-20 09:19:57 -0800119 DestOperandMap(DestMap), IsCompressOnly(IsCompressOnly) {}
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000120 };
Ana Pazosead53f62019-12-16 15:09:48 -0800121 enum EmitterType { Compress, Uncompress, CheckCompress };
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000122 RecordKeeper &Records;
123 CodeGenTarget Target;
124 SmallVector<CompressPat, 4> CompressPatterns;
125
126 void addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Inst,
127 IndexedMap<OpData> &OperandMap, bool IsSourceInst);
128 void evaluateCompressPat(Record *Compress);
Ana Pazosead53f62019-12-16 15:09:48 -0800129 void emitCompressInstEmitter(raw_ostream &o, EmitterType EType);
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000130 bool validateTypes(Record *SubType, Record *Type, bool IsSourceInst);
131 bool validateRegister(Record *Reg, Record *RegClass);
132 void createDagOperandMapping(Record *Rec, StringMap<unsigned> &SourceOperands,
133 StringMap<unsigned> &DestOperands,
134 DagInit *SourceDag, DagInit *DestDag,
135 IndexedMap<OpData> &SourceOperandMap);
136
137 void createInstOperandMapping(Record *Rec, DagInit *SourceDag,
138 DagInit *DestDag,
139 IndexedMap<OpData> &SourceOperandMap,
140 IndexedMap<OpData> &DestOperandMap,
141 StringMap<unsigned> &SourceOperands,
142 CodeGenInstruction &DestInst);
143
144public:
Zi Xuan Wucb380722021-11-18 10:22:21 +0800145 CompressInstEmitter(RecordKeeper &R) : Records(R), Target(R) {}
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000146
147 void run(raw_ostream &o);
148};
149} // End anonymous namespace.
150
Zi Xuan Wucb380722021-11-18 10:22:21 +0800151bool CompressInstEmitter::validateRegister(Record *Reg, Record *RegClass) {
Craig Topper4c2c1a52021-01-16 00:03:35 -0800152 assert(Reg->isSubClassOf("Register") && "Reg record should be a Register");
153 assert(RegClass->isSubClassOf("RegisterClass") &&
154 "RegClass record should be a RegisterClass");
Matt Arsenault57a98b42020-01-14 13:01:46 -0500155 const CodeGenRegisterClass &RC = Target.getRegisterClass(RegClass);
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000156 const CodeGenRegister *R = Target.getRegisterByName(Reg->getName().lower());
Craig Topper4c2c1a52021-01-16 00:03:35 -0800157 assert((R != nullptr) && "Register not defined!!");
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000158 return RC.contains(R);
159}
160
Zi Xuan Wucb380722021-11-18 10:22:21 +0800161bool CompressInstEmitter::validateTypes(Record *DagOpType, Record *InstOpType,
162 bool IsSourceInst) {
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000163 if (DagOpType == InstOpType)
164 return true;
165 // Only source instruction operands are allowed to not match Input Dag
166 // operands.
167 if (!IsSourceInst)
168 return false;
169
170 if (DagOpType->isSubClassOf("RegisterClass") &&
171 InstOpType->isSubClassOf("RegisterClass")) {
Matt Arsenault57a98b42020-01-14 13:01:46 -0500172 const CodeGenRegisterClass &RC = Target.getRegisterClass(InstOpType);
173 const CodeGenRegisterClass &SubRC = Target.getRegisterClass(DagOpType);
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000174 return RC.hasSubClass(&SubRC);
175 }
176
177 // At this point either or both types are not registers, reject the pattern.
178 if (DagOpType->isSubClassOf("RegisterClass") ||
179 InstOpType->isSubClassOf("RegisterClass"))
180 return false;
181
182 // Let further validation happen when compress()/uncompress() functions are
183 // invoked.
Nicola Zaghen54f49792018-05-14 12:53:11 +0000184 LLVM_DEBUG(dbgs() << (IsSourceInst ? "Input" : "Output")
185 << " Dag Operand Type: '" << DagOpType->getName()
186 << "' and "
187 << "Instruction Operand Type: '" << InstOpType->getName()
188 << "' can't be checked at pattern validation time!\n");
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000189 return true;
190}
191
192/// The patterns in the Dag contain different types of operands:
193/// Register operands, e.g.: GPRC:$rs1; Fixed registers, e.g: X1; Immediate
194/// operands, e.g.: simm6:$imm; Fixed immediate operands, e.g.: 0. This function
195/// maps Dag operands to its corresponding instruction operands. For register
196/// operands and fixed registers it expects the Dag operand type to be contained
197/// in the instantiated instruction operand type. For immediate operands and
198/// immediates no validation checks are enforced at pattern validation time.
Zi Xuan Wucb380722021-11-18 10:22:21 +0800199void CompressInstEmitter::addDagOperandMapping(Record *Rec, DagInit *Dag,
200 CodeGenInstruction &Inst,
201 IndexedMap<OpData> &OperandMap,
202 bool IsSourceInst) {
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000203 // TiedCount keeps track of the number of operands skipped in Inst
204 // operands list to get to the corresponding Dag operand. This is
205 // necessary because the number of operands in Inst might be greater
206 // than number of operands in the Dag due to how tied operands
207 // are represented.
208 unsigned TiedCount = 0;
209 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
210 int TiedOpIdx = Inst.Operands[i].getTiedRegister();
211 if (-1 != TiedOpIdx) {
212 // Set the entry in OperandMap for the tied operand we're skipping.
213 OperandMap[i].Kind = OperandMap[TiedOpIdx].Kind;
214 OperandMap[i].Data = OperandMap[TiedOpIdx].Data;
215 TiedCount++;
216 continue;
217 }
218 if (DefInit *DI = dyn_cast<DefInit>(Dag->getArg(i - TiedCount))) {
219 if (DI->getDef()->isSubClassOf("Register")) {
220 // Check if the fixed register belongs to the Register class.
221 if (!validateRegister(DI->getDef(), Inst.Operands[i].Rec))
222 PrintFatalError(Rec->getLoc(),
223 "Error in Dag '" + Dag->getAsString() +
224 "'Register: '" + DI->getDef()->getName() +
225 "' is not in register class '" +
226 Inst.Operands[i].Rec->getName() + "'");
227 OperandMap[i].Kind = OpData::Reg;
228 OperandMap[i].Data.Reg = DI->getDef();
229 continue;
230 }
231 // Validate that Dag operand type matches the type defined in the
232 // corresponding instruction. Operands in the input Dag pattern are
233 // allowed to be a subclass of the type specified in corresponding
234 // instruction operand instead of being an exact match.
235 if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst))
236 PrintFatalError(Rec->getLoc(),
237 "Error in Dag '" + Dag->getAsString() + "'. Operand '" +
238 Dag->getArgNameStr(i - TiedCount) + "' has type '" +
239 DI->getDef()->getName() +
240 "' which does not match the type '" +
241 Inst.Operands[i].Rec->getName() +
242 "' in the corresponding instruction operand!");
243
244 OperandMap[i].Kind = OpData::Operand;
245 } else if (IntInit *II = dyn_cast<IntInit>(Dag->getArg(i - TiedCount))) {
246 // Validate that corresponding instruction operand expects an immediate.
247 if (Inst.Operands[i].Rec->isSubClassOf("RegisterClass"))
248 PrintFatalError(
249 Rec->getLoc(),
Craig Topper4c2c1a52021-01-16 00:03:35 -0800250 "Error in Dag '" + Dag->getAsString() + "' Found immediate: '" +
251 II->getAsString() +
252 "' but corresponding instruction operand expected a register!");
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000253 // No pattern validation check possible for values of fixed immediate.
254 OperandMap[i].Kind = OpData::Imm;
255 OperandMap[i].Data.Imm = II->getValue();
Nicola Zaghen54f49792018-05-14 12:53:11 +0000256 LLVM_DEBUG(
257 dbgs() << " Found immediate '" << II->getValue() << "' at "
258 << (IsSourceInst ? "input " : "output ")
259 << "Dag. No validation time check possible for values of "
260 "fixed immediate.\n");
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000261 } else
262 llvm_unreachable("Unhandled CompressPat argument type!");
263 }
264}
265
266// Verify the Dag operand count is enough to build an instruction.
267static bool verifyDagOpCount(CodeGenInstruction &Inst, DagInit *Dag,
268 bool IsSource) {
269 if (Dag->getNumArgs() == Inst.Operands.size())
270 return true;
271 // Source instructions are non compressed instructions and don't have tied
272 // operands.
273 if (IsSource)
Daniel Sanders73ac4682019-02-12 17:36:57 +0000274 PrintFatalError(Inst.TheDef->getLoc(),
275 "Input operands for Inst '" + Inst.TheDef->getName() +
276 "' and input Dag operand count mismatch");
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000277 // The Dag can't have more arguments than the Instruction.
278 if (Dag->getNumArgs() > Inst.Operands.size())
Daniel Sanders73ac4682019-02-12 17:36:57 +0000279 PrintFatalError(Inst.TheDef->getLoc(),
280 "Inst '" + Inst.TheDef->getName() +
281 "' and Dag operand count mismatch");
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000282
283 // The Instruction might have tied operands so the Dag might have
284 // a fewer operand count.
285 unsigned RealCount = Inst.Operands.size();
Coelacanthus4d992f32021-05-06 18:36:52 +0800286 for (const auto &Operand : Inst.Operands)
287 if (Operand.getTiedRegister() != -1)
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000288 --RealCount;
289
290 if (Dag->getNumArgs() != RealCount)
Daniel Sanders73ac4682019-02-12 17:36:57 +0000291 PrintFatalError(Inst.TheDef->getLoc(),
292 "Inst '" + Inst.TheDef->getName() +
293 "' and Dag operand count mismatch");
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000294 return true;
295}
296
297static bool validateArgsTypes(Init *Arg1, Init *Arg2) {
Craig Topper2f7b71c2021-01-16 20:23:41 -0800298 return cast<DefInit>(Arg1)->getDef() == cast<DefInit>(Arg2)->getDef();
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000299}
300
301// Creates a mapping between the operand name in the Dag (e.g. $rs1) and
302// its index in the list of Dag operands and checks that operands with the same
303// name have the same types. For example in 'C_ADD $rs1, $rs2' we generate the
304// mapping $rs1 --> 0, $rs2 ---> 1. If the operand appears twice in the (tied)
305// same Dag we use the last occurrence for indexing.
Zi Xuan Wucb380722021-11-18 10:22:21 +0800306void CompressInstEmitter::createDagOperandMapping(
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000307 Record *Rec, StringMap<unsigned> &SourceOperands,
308 StringMap<unsigned> &DestOperands, DagInit *SourceDag, DagInit *DestDag,
309 IndexedMap<OpData> &SourceOperandMap) {
310 for (unsigned i = 0; i < DestDag->getNumArgs(); ++i) {
311 // Skip fixed immediates and registers, they were handled in
312 // addDagOperandMapping.
313 if ("" == DestDag->getArgNameStr(i))
314 continue;
315 DestOperands[DestDag->getArgNameStr(i)] = i;
316 }
317
318 for (unsigned i = 0; i < SourceDag->getNumArgs(); ++i) {
319 // Skip fixed immediates and registers, they were handled in
320 // addDagOperandMapping.
321 if ("" == SourceDag->getArgNameStr(i))
322 continue;
323
324 StringMap<unsigned>::iterator it =
325 SourceOperands.find(SourceDag->getArgNameStr(i));
326 if (it != SourceOperands.end()) {
327 // Operand sharing the same name in the Dag should be mapped as tied.
328 SourceOperandMap[i].TiedOpIdx = it->getValue();
329 if (!validateArgsTypes(SourceDag->getArg(it->getValue()),
330 SourceDag->getArg(i)))
331 PrintFatalError(Rec->getLoc(),
332 "Input Operand '" + SourceDag->getArgNameStr(i) +
333 "' has a mismatched tied operand!\n");
334 }
335 it = DestOperands.find(SourceDag->getArgNameStr(i));
336 if (it == DestOperands.end())
337 PrintFatalError(Rec->getLoc(), "Operand " + SourceDag->getArgNameStr(i) +
338 " defined in Input Dag but not used in"
339 " Output Dag!\n");
340 // Input Dag operand types must match output Dag operand type.
341 if (!validateArgsTypes(DestDag->getArg(it->getValue()),
342 SourceDag->getArg(i)))
343 PrintFatalError(Rec->getLoc(), "Type mismatch between Input and "
344 "Output Dag operand '" +
345 SourceDag->getArgNameStr(i) + "'!");
346 SourceOperands[SourceDag->getArgNameStr(i)] = i;
347 }
348}
349
350/// Map operand names in the Dag to their index in both corresponding input and
351/// output instructions. Validate that operands defined in the input are
352/// used in the output pattern while populating the maps.
Zi Xuan Wucb380722021-11-18 10:22:21 +0800353void CompressInstEmitter::createInstOperandMapping(
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000354 Record *Rec, DagInit *SourceDag, DagInit *DestDag,
355 IndexedMap<OpData> &SourceOperandMap, IndexedMap<OpData> &DestOperandMap,
356 StringMap<unsigned> &SourceOperands, CodeGenInstruction &DestInst) {
357 // TiedCount keeps track of the number of operands skipped in Inst
358 // operands list to get to the corresponding Dag operand.
359 unsigned TiedCount = 0;
Nicola Zaghen54f49792018-05-14 12:53:11 +0000360 LLVM_DEBUG(dbgs() << " Operand mapping:\n Source Dest\n");
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000361 for (unsigned i = 0, e = DestInst.Operands.size(); i != e; ++i) {
362 int TiedInstOpIdx = DestInst.Operands[i].getTiedRegister();
363 if (TiedInstOpIdx != -1) {
364 ++TiedCount;
365 DestOperandMap[i].Data = DestOperandMap[TiedInstOpIdx].Data;
366 DestOperandMap[i].Kind = DestOperandMap[TiedInstOpIdx].Kind;
367 if (DestOperandMap[i].Kind == OpData::Operand)
368 // No need to fill the SourceOperandMap here since it was mapped to
369 // destination operand 'TiedInstOpIdx' in a previous iteration.
Nicola Zaghen54f49792018-05-14 12:53:11 +0000370 LLVM_DEBUG(dbgs() << " " << DestOperandMap[i].Data.Operand
371 << " ====> " << i
372 << " Dest operand tied with operand '"
373 << TiedInstOpIdx << "'\n");
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000374 continue;
375 }
376 // Skip fixed immediates and registers, they were handled in
377 // addDagOperandMapping.
378 if (DestOperandMap[i].Kind != OpData::Operand)
379 continue;
380
381 unsigned DagArgIdx = i - TiedCount;
382 StringMap<unsigned>::iterator SourceOp =
383 SourceOperands.find(DestDag->getArgNameStr(DagArgIdx));
384 if (SourceOp == SourceOperands.end())
385 PrintFatalError(Rec->getLoc(),
386 "Output Dag operand '" +
387 DestDag->getArgNameStr(DagArgIdx) +
388 "' has no matching input Dag operand.");
389
390 assert(DestDag->getArgNameStr(DagArgIdx) ==
391 SourceDag->getArgNameStr(SourceOp->getValue()) &&
392 "Incorrect operand mapping detected!\n");
393 DestOperandMap[i].Data.Operand = SourceOp->getValue();
394 SourceOperandMap[SourceOp->getValue()].Data.Operand = i;
Nicola Zaghen54f49792018-05-14 12:53:11 +0000395 LLVM_DEBUG(dbgs() << " " << SourceOp->getValue() << " ====> " << i
396 << "\n");
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000397 }
398}
399
400/// Validates the CompressPattern and create operand mapping.
401/// These are the checks to validate a CompressPat pattern declarations.
402/// Error out with message under these conditions:
403/// - Dag Input opcode is an expanded instruction and Dag Output opcode is a
404/// compressed instruction.
405/// - Operands in Dag Input must be all used in Dag Output.
406/// Register Operand type in Dag Input Type must be contained in the
407/// corresponding Source Instruction type.
408/// - Register Operand type in Dag Input must be the same as in Dag Ouput.
409/// - Register Operand type in Dag Output must be the same as the
410/// corresponding Destination Inst type.
411/// - Immediate Operand type in Dag Input must be the same as in Dag Ouput.
412/// - Immediate Operand type in Dag Ouput must be the same as the corresponding
413/// Destination Instruction type.
414/// - Fixed register must be contained in the corresponding Source Instruction
415/// type.
416/// - Fixed register must be contained in the corresponding Destination
417/// Instruction type. Warning message printed under these conditions:
418/// - Fixed immediate in Dag Input or Dag Ouput cannot be checked at this time
419/// and generate warning.
420/// - Immediate operand type in Dag Input differs from the corresponding Source
421/// Instruction type and generate a warning.
Zi Xuan Wucb380722021-11-18 10:22:21 +0800422void CompressInstEmitter::evaluateCompressPat(Record *Rec) {
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000423 // Validate input Dag operands.
424 DagInit *SourceDag = Rec->getValueAsDag("Input");
425 assert(SourceDag && "Missing 'Input' in compress pattern!");
Nicola Zaghen54f49792018-05-14 12:53:11 +0000426 LLVM_DEBUG(dbgs() << "Input: " << *SourceDag << "\n");
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000427
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000428 // Checking we are transforming from compressed to uncompressed instructions.
Daniel Sandersc8c79e92019-10-08 18:41:32 +0000429 Record *Operator = SourceDag->getOperatorAsDef(Rec->getLoc());
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000430 CodeGenInstruction SourceInst(Operator);
431 verifyDagOpCount(SourceInst, SourceDag, true);
432
433 // Validate output Dag operands.
434 DagInit *DestDag = Rec->getValueAsDag("Output");
435 assert(DestDag && "Missing 'Output' in compress pattern!");
Nicola Zaghen54f49792018-05-14 12:53:11 +0000436 LLVM_DEBUG(dbgs() << "Output: " << *DestDag << "\n");
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000437
Daniel Sandersc8c79e92019-10-08 18:41:32 +0000438 Record *DestOperator = DestDag->getOperatorAsDef(Rec->getLoc());
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000439 CodeGenInstruction DestInst(DestOperator);
440 verifyDagOpCount(DestInst, DestDag, false);
441
Zi Xuan Wucb380722021-11-18 10:22:21 +0800442 if (Operator->getValueAsInt("Size") <= DestOperator->getValueAsInt("Size"))
443 PrintFatalError(
444 Rec->getLoc(),
445 "Compressed instruction '" + DestOperator->getName() +
446 "'is not strictly smaller than the uncompressed instruction '" +
447 Operator->getName() + "' !");
448
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000449 // Fill the mapping from the source to destination instructions.
450
451 IndexedMap<OpData> SourceOperandMap;
452 SourceOperandMap.grow(SourceInst.Operands.size());
453 // Create a mapping between source Dag operands and source Inst operands.
454 addDagOperandMapping(Rec, SourceDag, SourceInst, SourceOperandMap,
455 /*IsSourceInst*/ true);
456
457 IndexedMap<OpData> DestOperandMap;
458 DestOperandMap.grow(DestInst.Operands.size());
459 // Create a mapping between destination Dag operands and destination Inst
460 // operands.
461 addDagOperandMapping(Rec, DestDag, DestInst, DestOperandMap,
462 /*IsSourceInst*/ false);
463
464 StringMap<unsigned> SourceOperands;
465 StringMap<unsigned> DestOperands;
466 createDagOperandMapping(Rec, SourceOperands, DestOperands, SourceDag, DestDag,
467 SourceOperandMap);
468 // Create operand mapping between the source and destination instructions.
469 createInstOperandMapping(Rec, SourceDag, DestDag, SourceOperandMap,
470 DestOperandMap, SourceOperands, DestInst);
471
472 // Get the target features for the CompressPat.
473 std::vector<Record *> PatReqFeatures;
474 std::vector<Record *> RF = Rec->getValueAsListOfDefs("Predicates");
475 copy_if(RF, std::back_inserter(PatReqFeatures), [](Record *R) {
476 return R->getValueAsBit("AssemblerMatcherPredicate");
477 });
478
479 CompressPatterns.push_back(CompressPat(SourceInst, DestInst, PatReqFeatures,
Craig Topper0d57e1d2021-01-20 09:19:57 -0800480 SourceOperandMap, DestOperandMap,
481 Rec->getValueAsBit("isCompressOnly")));
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000482}
483
Simon Cookd7ca48f2020-03-13 17:13:51 +0000484static void
485getReqFeatures(std::set<std::pair<bool, StringRef>> &FeaturesSet,
486 std::set<std::set<std::pair<bool, StringRef>>> &AnyOfFeatureSets,
487 const std::vector<Record *> &ReqFeatures) {
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000488 for (auto &R : ReqFeatures) {
Simon Cookd7ca48f2020-03-13 17:13:51 +0000489 const DagInit *D = R->getValueAsDag("AssemblerCondDag");
490 std::string CombineType = D->getOperator()->getAsString();
491 if (CombineType != "any_of" && CombineType != "all_of")
492 PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
493 if (D->getNumArgs() == 0)
494 PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
495 bool IsOr = CombineType == "any_of";
496 std::set<std::pair<bool, StringRef>> AnyOfSet;
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000497
Simon Cookd7ca48f2020-03-13 17:13:51 +0000498 for (auto *Arg : D->getArgs()) {
499 bool IsNot = false;
500 if (auto *NotArg = dyn_cast<DagInit>(Arg)) {
501 if (NotArg->getOperator()->getAsString() != "not" ||
502 NotArg->getNumArgs() != 1)
503 PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
504 Arg = NotArg->getArg(0);
505 IsNot = true;
506 }
507 if (!isa<DefInit>(Arg) ||
508 !cast<DefInit>(Arg)->getDef()->isSubClassOf("SubtargetFeature"))
509 PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!");
510 if (IsOr)
511 AnyOfSet.insert({IsNot, cast<DefInit>(Arg)->getDef()->getName()});
512 else
513 FeaturesSet.insert({IsNot, cast<DefInit>(Arg)->getDef()->getName()});
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000514 }
Simon Cookd7ca48f2020-03-13 17:13:51 +0000515
516 if (IsOr)
517 AnyOfFeatureSets.insert(AnyOfSet);
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000518 }
519}
520
Ana Pazosead53f62019-12-16 15:09:48 -0800521static unsigned getPredicates(DenseMap<const Record *, unsigned> &PredicateMap,
522 std::vector<const Record *> &Predicates,
523 Record *Rec, StringRef Name) {
Craig Topper0fe15a62021-01-16 21:18:52 -0800524 unsigned &Entry = PredicateMap[Rec];
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000525 if (Entry)
526 return Entry;
527
Ana Pazosead53f62019-12-16 15:09:48 -0800528 if (!Rec->isValueUnset(Name)) {
529 Predicates.push_back(Rec);
530 Entry = Predicates.size();
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000531 return Entry;
532 }
533
Ana Pazosead53f62019-12-16 15:09:48 -0800534 PrintFatalError(Rec->getLoc(), "No " + Name +
Craig Topper4c2c1a52021-01-16 00:03:35 -0800535 " predicate on this operand at all: '" +
536 Rec->getName() + "'");
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000537 return 0;
538}
539
Craig Topperd9456ed2021-01-16 21:09:37 -0800540static void printPredicates(const std::vector<const Record *> &Predicates,
Ana Pazosead53f62019-12-16 15:09:48 -0800541 StringRef Name, raw_ostream &o) {
542 for (unsigned i = 0; i < Predicates.size(); ++i) {
Paul C. Anagnostopoulosb67ea6c2020-11-24 13:09:02 -0500543 StringRef Pred = Predicates[i]->getValueAsString(Name);
544 o << " case " << i + 1 << ": {\n"
Craig Topper4c2c1a52021-01-16 00:03:35 -0800545 << " // " << Predicates[i]->getName() << "\n"
Craig Topperd9456ed2021-01-16 21:09:37 -0800546 << " " << Pred << "\n"
Paul C. Anagnostopoulosb67ea6c2020-11-24 13:09:02 -0500547 << " }\n";
Ana Pazosead53f62019-12-16 15:09:48 -0800548 }
549}
550
Craig Topper98f00622021-01-16 20:59:48 -0800551static void mergeCondAndCode(raw_ostream &CombinedStream, StringRef CondStr,
552 StringRef CodeStr) {
553 // Remove first indentation and last '&&'.
554 CondStr = CondStr.drop_front(6).drop_back(4);
555 CombinedStream.indent(4) << "if (" << CondStr << ") {\n";
556 CombinedStream << CodeStr;
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000557 CombinedStream.indent(4) << " return true;\n";
558 CombinedStream.indent(4) << "} // if\n";
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000559}
560
Zi Xuan Wucb380722021-11-18 10:22:21 +0800561void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
562 EmitterType EType) {
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000563 Record *AsmWriter = Target.getAsmWriter();
564 if (!AsmWriter->getValueAsInt("PassSubtarget"))
Daniel Sanders73ac4682019-02-12 17:36:57 +0000565 PrintFatalError(AsmWriter->getLoc(),
566 "'PassSubtarget' is false. SubTargetInfo object is needed "
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000567 "for target features.\n");
568
Zi Xuan Wucb380722021-11-18 10:22:21 +0800569 StringRef TargetName = Target.getName();
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000570
571 // Sort entries in CompressPatterns to handle instructions that can have more
572 // than one candidate for compression\uncompression, e.g ADD can be
573 // transformed to a C_ADD or a C_MV. When emitting 'uncompress()' function the
574 // source and destination are flipped and the sort key needs to change
575 // accordingly.
Craig Topper4c2c1a52021-01-16 00:03:35 -0800576 llvm::stable_sort(CompressPatterns, [EType](const CompressPat &LHS,
577 const CompressPat &RHS) {
578 if (EType == EmitterType::Compress || EType == EmitterType::CheckCompress)
579 return (LHS.Source.TheDef->getName() < RHS.Source.TheDef->getName());
580 else
581 return (LHS.Dest.TheDef->getName() < RHS.Dest.TheDef->getName());
582 });
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000583
584 // A list of MCOperandPredicates for all operands in use, and the reverse map.
585 std::vector<const Record *> MCOpPredicates;
586 DenseMap<const Record *, unsigned> MCOpPredicateMap;
Ana Pazosead53f62019-12-16 15:09:48 -0800587 // A list of ImmLeaf Predicates for all operands in use, and the reverse map.
588 std::vector<const Record *> ImmLeafPredicates;
589 DenseMap<const Record *, unsigned> ImmLeafPredicateMap;
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000590
591 std::string F;
592 std::string FH;
593 raw_string_ostream Func(F);
594 raw_string_ostream FuncH(FH);
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000595
Ana Pazosead53f62019-12-16 15:09:48 -0800596 if (EType == EmitterType::Compress)
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000597 o << "\n#ifdef GEN_COMPRESS_INSTR\n"
598 << "#undef GEN_COMPRESS_INSTR\n\n";
Ana Pazosead53f62019-12-16 15:09:48 -0800599 else if (EType == EmitterType::Uncompress)
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000600 o << "\n#ifdef GEN_UNCOMPRESS_INSTR\n"
601 << "#undef GEN_UNCOMPRESS_INSTR\n\n";
Ana Pazosead53f62019-12-16 15:09:48 -0800602 else if (EType == EmitterType::CheckCompress)
603 o << "\n#ifdef GEN_CHECK_COMPRESS_INSTR\n"
604 << "#undef GEN_CHECK_COMPRESS_INSTR\n\n";
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000605
Ana Pazosead53f62019-12-16 15:09:48 -0800606 if (EType == EmitterType::Compress) {
Jay Foad94474cd2020-11-06 14:19:59 +0000607 FuncH << "static bool compressInst(MCInst &OutInst,\n";
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000608 FuncH.indent(25) << "const MCInst &MI,\n";
Craig Topper53801ff2023-01-17 11:50:54 -0800609 FuncH.indent(25) << "const MCSubtargetInfo &STI) {\n";
Zi Xuan Wucb380722021-11-18 10:22:21 +0800610 } else if (EType == EmitterType::Uncompress) {
Jay Foad94474cd2020-11-06 14:19:59 +0000611 FuncH << "static bool uncompressInst(MCInst &OutInst,\n";
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000612 FuncH.indent(27) << "const MCInst &MI,\n";
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000613 FuncH.indent(27) << "const MCSubtargetInfo &STI) {\n";
Ana Pazosead53f62019-12-16 15:09:48 -0800614 } else if (EType == EmitterType::CheckCompress) {
Jay Foad94474cd2020-11-06 14:19:59 +0000615 FuncH << "static bool isCompressibleInst(const MachineInstr &MI,\n";
Craig Topper47afb8f2023-01-17 18:04:55 -0800616 FuncH.indent(31) << "const " << TargetName << "Subtarget &STI) {\n";
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000617 }
618
619 if (CompressPatterns.empty()) {
620 o << FuncH.str();
621 o.indent(2) << "return false;\n}\n";
Ana Pazosead53f62019-12-16 15:09:48 -0800622 if (EType == EmitterType::Compress)
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000623 o << "\n#endif //GEN_COMPRESS_INSTR\n";
Ana Pazosead53f62019-12-16 15:09:48 -0800624 else if (EType == EmitterType::Uncompress)
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000625 o << "\n#endif //GEN_UNCOMPRESS_INSTR\n\n";
Ana Pazosead53f62019-12-16 15:09:48 -0800626 else if (EType == EmitterType::CheckCompress)
627 o << "\n#endif //GEN_CHECK_COMPRESS_INSTR\n\n";
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000628 return;
629 }
630
Kazu Hiratad4861ce2021-01-12 21:43:46 -0800631 std::string CaseString;
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000632 raw_string_ostream CaseStream(CaseString);
Craig Topperd9456ed2021-01-16 21:09:37 -0800633 StringRef PrevOp;
634 StringRef CurOp;
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000635 CaseStream << " switch (MI.getOpcode()) {\n";
636 CaseStream << " default: return false;\n";
637
Ana Pazosead53f62019-12-16 15:09:48 -0800638 bool CompressOrCheck =
Zi Xuan Wucb380722021-11-18 10:22:21 +0800639 EType == EmitterType::Compress || EType == EmitterType::CheckCompress;
Ana Pazosead53f62019-12-16 15:09:48 -0800640 bool CompressOrUncompress =
Zi Xuan Wucb380722021-11-18 10:22:21 +0800641 EType == EmitterType::Compress || EType == EmitterType::Uncompress;
wangpc9d805ec2023-01-18 14:24:03 +0800642 std::string ValidatorName =
643 CompressOrUncompress
644 ? (TargetName + "ValidateMCOperandFor" +
645 (EType == EmitterType::Compress ? "Compress" : "Uncompress"))
646 .str()
647 : "";
Ana Pazosead53f62019-12-16 15:09:48 -0800648
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000649 for (auto &CompressPat : CompressPatterns) {
Craig Topper0d57e1d2021-01-20 09:19:57 -0800650 if (EType == EmitterType::Uncompress && CompressPat.IsCompressOnly)
651 continue;
652
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000653 std::string CondString;
654 std::string CodeString;
655 raw_string_ostream CondStream(CondString);
656 raw_string_ostream CodeStream(CodeString);
657 CodeGenInstruction &Source =
Zi Xuan Wucb380722021-11-18 10:22:21 +0800658 CompressOrCheck ? CompressPat.Source : CompressPat.Dest;
Ana Pazosead53f62019-12-16 15:09:48 -0800659 CodeGenInstruction &Dest =
660 CompressOrCheck ? CompressPat.Dest : CompressPat.Source;
Zi Xuan Wucb380722021-11-18 10:22:21 +0800661 IndexedMap<OpData> SourceOperandMap = CompressOrCheck
662 ? CompressPat.SourceOperandMap
663 : CompressPat.DestOperandMap;
664 IndexedMap<OpData> &DestOperandMap = CompressOrCheck
665 ? CompressPat.DestOperandMap
666 : CompressPat.SourceOperandMap;
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000667
Craig Topperd9456ed2021-01-16 21:09:37 -0800668 CurOp = Source.TheDef->getName();
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000669 // Check current and previous opcode to decide to continue or end a case.
670 if (CurOp != PrevOp) {
Craig Topperd9456ed2021-01-16 21:09:37 -0800671 if (!PrevOp.empty())
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000672 CaseStream.indent(6) << "break;\n } // case " + PrevOp + "\n";
Zi Xuan Wucb380722021-11-18 10:22:21 +0800673 CaseStream.indent(4) << "case " + TargetName + "::" + CurOp + ": {\n";
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000674 }
675
Simon Cookd7ca48f2020-03-13 17:13:51 +0000676 std::set<std::pair<bool, StringRef>> FeaturesSet;
677 std::set<std::set<std::pair<bool, StringRef>>> AnyOfFeatureSets;
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000678 // Add CompressPat required features.
Simon Cookd7ca48f2020-03-13 17:13:51 +0000679 getReqFeatures(FeaturesSet, AnyOfFeatureSets, CompressPat.PatReqFeatures);
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000680
681 // Add Dest instruction required features.
682 std::vector<Record *> ReqFeatures;
683 std::vector<Record *> RF = Dest.TheDef->getValueAsListOfDefs("Predicates");
684 copy_if(RF, std::back_inserter(ReqFeatures), [](Record *R) {
685 return R->getValueAsBit("AssemblerMatcherPredicate");
686 });
Simon Cookd7ca48f2020-03-13 17:13:51 +0000687 getReqFeatures(FeaturesSet, AnyOfFeatureSets, ReqFeatures);
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000688
689 // Emit checks for all required features.
Sameer AbuAsalbbf18112019-06-10 17:15:45 +0000690 for (auto &Op : FeaturesSet) {
Simon Cookd7ca48f2020-03-13 17:13:51 +0000691 StringRef Not = Op.first ? "!" : "";
Zi Xuan Wucb380722021-11-18 10:22:21 +0800692 CondStream.indent(6) << Not << "STI.getFeatureBits()[" << TargetName
Craig Topper4c2c1a52021-01-16 00:03:35 -0800693 << "::" << Op.second << "]"
694 << " &&\n";
Simon Cookd7ca48f2020-03-13 17:13:51 +0000695 }
696
697 // Emit checks for all required feature groups.
698 for (auto &Set : AnyOfFeatureSets) {
699 CondStream.indent(6) << "(";
700 for (auto &Op : Set) {
701 bool isLast = &Op == &*Set.rbegin();
702 StringRef Not = Op.first ? "!" : "";
Zi Xuan Wucb380722021-11-18 10:22:21 +0800703 CondStream << Not << "STI.getFeatureBits()[" << TargetName
Craig Topper4c2c1a52021-01-16 00:03:35 -0800704 << "::" << Op.second << "]";
Simon Cookd7ca48f2020-03-13 17:13:51 +0000705 if (!isLast)
706 CondStream << " || ";
707 }
708 CondStream << ") &&\n";
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000709 }
710
711 // Start Source Inst operands validation.
712 unsigned OpNo = 0;
713 for (OpNo = 0; OpNo < Source.Operands.size(); ++OpNo) {
714 if (SourceOperandMap[OpNo].TiedOpIdx != -1) {
715 if (Source.Operands[OpNo].Rec->isSubClassOf("RegisterClass"))
716 CondStream.indent(6)
ZHU Zijia3f56b3b2022-08-24 13:23:38 +0800717 << "(MI.getOperand(" << OpNo << ").isReg()) && (MI.getOperand("
718 << SourceOperandMap[OpNo].TiedOpIdx << ").isReg()) &&\n"
719 << " (MI.getOperand(" << OpNo
720 << ").getReg() == MI.getOperand("
Craig Topper4c2c1a52021-01-16 00:03:35 -0800721 << SourceOperandMap[OpNo].TiedOpIdx << ").getReg()) &&\n";
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000722 else
723 PrintFatalError("Unexpected tied operand types!\n");
724 }
725 // Check for fixed immediates\registers in the source instruction.
726 switch (SourceOperandMap[OpNo].Kind) {
727 case OpData::Operand:
728 // We don't need to do anything for source instruction operand checks.
729 break;
730 case OpData::Imm:
731 CondStream.indent(6)
Craig Topper4c2c1a52021-01-16 00:03:35 -0800732 << "(MI.getOperand(" << OpNo << ").isImm()) &&\n"
733 << " (MI.getOperand(" << OpNo
734 << ").getImm() == " << SourceOperandMap[OpNo].Data.Imm << ") &&\n";
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000735 break;
736 case OpData::Reg: {
737 Record *Reg = SourceOperandMap[OpNo].Data.Reg;
Craig Topper4c2c1a52021-01-16 00:03:35 -0800738 CondStream.indent(6)
ZHU Zijia3f56b3b2022-08-24 13:23:38 +0800739 << "(MI.getOperand(" << OpNo << ").isReg()) &&\n"
740 << " (MI.getOperand(" << OpNo << ").getReg() == " << TargetName
Craig Topper4c2c1a52021-01-16 00:03:35 -0800741 << "::" << Reg->getName() << ") &&\n";
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000742 break;
743 }
744 }
745 }
Craig Topper4c2c1a52021-01-16 00:03:35 -0800746 CodeStream.indent(6) << "// " << Dest.AsmString << "\n";
Ana Pazosead53f62019-12-16 15:09:48 -0800747 if (CompressOrUncompress)
Zi Xuan Wucb380722021-11-18 10:22:21 +0800748 CodeStream.indent(6) << "OutInst.setOpcode(" << TargetName
Craig Topper4c2c1a52021-01-16 00:03:35 -0800749 << "::" << Dest.TheDef->getName() << ");\n";
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000750 OpNo = 0;
751 for (const auto &DestOperand : Dest.Operands) {
Craig Topper4c2c1a52021-01-16 00:03:35 -0800752 CodeStream.indent(6) << "// Operand: " << DestOperand.Name << "\n";
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000753 switch (DestOperandMap[OpNo].Kind) {
754 case OpData::Operand: {
755 unsigned OpIdx = DestOperandMap[OpNo].Data.Operand;
756 // Check that the operand in the Source instruction fits
757 // the type for the Dest instruction.
Dmitry Busheve50b0f72022-11-22 14:52:10 +0300758 if (DestOperand.Rec->isSubClassOf("RegisterClass") ||
759 DestOperand.Rec->isSubClassOf("RegisterOperand")) {
760 auto *ClassRec = DestOperand.Rec->isSubClassOf("RegisterClass")
761 ? DestOperand.Rec
762 : DestOperand.Rec->getValueAsDef("RegClass");
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000763 // This is a register operand. Check the register class.
764 // Don't check register class if this is a tied operand, it was done
765 // for the operand its tied to.
766 if (DestOperand.getTiedRegister() == -1)
ZHU Zijia3f56b3b2022-08-24 13:23:38 +0800767 CondStream.indent(6)
768 << "(MI.getOperand(" << OpIdx << ").isReg()) &&\n"
Craig Topper53801ff2023-01-17 11:50:54 -0800769 << " (" << TargetName << "MCRegisterClasses["
770 << TargetName << "::" << ClassRec->getName()
771 << "RegClassID].contains(MI.getOperand(" << OpIdx
ZHU Zijia3f56b3b2022-08-24 13:23:38 +0800772 << ").getReg())) &&\n";
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000773
Ana Pazosead53f62019-12-16 15:09:48 -0800774 if (CompressOrUncompress)
Craig Topper4c2c1a52021-01-16 00:03:35 -0800775 CodeStream.indent(6)
776 << "OutInst.addOperand(MI.getOperand(" << OpIdx << "));\n";
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000777 } else {
778 // Handling immediate operands.
Ana Pazosead53f62019-12-16 15:09:48 -0800779 if (CompressOrUncompress) {
Craig Topper0fe15a62021-01-16 21:18:52 -0800780 unsigned Entry =
781 getPredicates(MCOpPredicateMap, MCOpPredicates, DestOperand.Rec,
782 "MCOperandPredicate");
Craig Topper4c2c1a52021-01-16 00:03:35 -0800783 CondStream.indent(6)
wangpc9d805ec2023-01-18 14:24:03 +0800784 << ValidatorName << "("
Craig Topper4c2c1a52021-01-16 00:03:35 -0800785 << "MI.getOperand(" << OpIdx << "), STI, " << Entry << ") &&\n";
Ana Pazosead53f62019-12-16 15:09:48 -0800786 } else {
Craig Topper0fe15a62021-01-16 21:18:52 -0800787 unsigned Entry =
788 getPredicates(ImmLeafPredicateMap, ImmLeafPredicates,
789 DestOperand.Rec, "ImmediateCode");
Craig Topper4c2c1a52021-01-16 00:03:35 -0800790 CondStream.indent(6)
791 << "MI.getOperand(" << OpIdx << ").isImm() &&\n";
Zi Xuan Wucb380722021-11-18 10:22:21 +0800792 CondStream.indent(6) << TargetName << "ValidateMachineOperand("
Craig Topper4c2c1a52021-01-16 00:03:35 -0800793 << "MI.getOperand(" << OpIdx
Craig Topper47afb8f2023-01-17 18:04:55 -0800794 << "), &STI, " << Entry << ") &&\n";
Ana Pazosead53f62019-12-16 15:09:48 -0800795 }
796 if (CompressOrUncompress)
Craig Topper4c2c1a52021-01-16 00:03:35 -0800797 CodeStream.indent(6)
798 << "OutInst.addOperand(MI.getOperand(" << OpIdx << "));\n";
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000799 }
800 break;
801 }
802 case OpData::Imm: {
Ana Pazosead53f62019-12-16 15:09:48 -0800803 if (CompressOrUncompress) {
804 unsigned Entry = getPredicates(MCOpPredicateMap, MCOpPredicates,
Craig Topper0fe15a62021-01-16 21:18:52 -0800805 DestOperand.Rec, "MCOperandPredicate");
Ana Pazosead53f62019-12-16 15:09:48 -0800806 CondStream.indent(6)
wangpc9d805ec2023-01-18 14:24:03 +0800807 << ValidatorName << "("
Craig Topper4c2c1a52021-01-16 00:03:35 -0800808 << "MCOperand::createImm(" << DestOperandMap[OpNo].Data.Imm
809 << "), STI, " << Entry << ") &&\n";
Ana Pazosead53f62019-12-16 15:09:48 -0800810 } else {
811 unsigned Entry = getPredicates(ImmLeafPredicateMap, ImmLeafPredicates,
Craig Topper0fe15a62021-01-16 21:18:52 -0800812 DestOperand.Rec, "ImmediateCode");
Ana Pazosead53f62019-12-16 15:09:48 -0800813 CondStream.indent(6)
Zi Xuan Wucb380722021-11-18 10:22:21 +0800814 << TargetName
Craig Topper4c2c1a52021-01-16 00:03:35 -0800815 << "ValidateMachineOperand(MachineOperand::CreateImm("
Craig Topper47afb8f2023-01-17 18:04:55 -0800816 << DestOperandMap[OpNo].Data.Imm << "), &STI, " << Entry
Craig Topper4c2c1a52021-01-16 00:03:35 -0800817 << ") &&\n";
Ana Pazosead53f62019-12-16 15:09:48 -0800818 }
819 if (CompressOrUncompress)
Craig Topper4c2c1a52021-01-16 00:03:35 -0800820 CodeStream.indent(6) << "OutInst.addOperand(MCOperand::createImm("
821 << DestOperandMap[OpNo].Data.Imm << "));\n";
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000822 } break;
823 case OpData::Reg: {
Ana Pazosead53f62019-12-16 15:09:48 -0800824 if (CompressOrUncompress) {
825 // Fixed register has been validated at pattern validation time.
826 Record *Reg = DestOperandMap[OpNo].Data.Reg;
Craig Topper4c2c1a52021-01-16 00:03:35 -0800827 CodeStream.indent(6)
Zi Xuan Wucb380722021-11-18 10:22:21 +0800828 << "OutInst.addOperand(MCOperand::createReg(" << TargetName
Craig Topper4c2c1a52021-01-16 00:03:35 -0800829 << "::" << Reg->getName() << "));\n";
Ana Pazosead53f62019-12-16 15:09:48 -0800830 }
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000831 } break;
832 }
833 ++OpNo;
834 }
Ana Pazosead53f62019-12-16 15:09:48 -0800835 if (CompressOrUncompress)
836 CodeStream.indent(6) << "OutInst.setLoc(MI.getLoc());\n";
Craig Topper98f00622021-01-16 20:59:48 -0800837 mergeCondAndCode(CaseStream, CondStream.str(), CodeStream.str());
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000838 PrevOp = CurOp;
839 }
840 Func << CaseStream.str() << "\n";
841 // Close brace for the last case.
Craig Topper4c2c1a52021-01-16 00:03:35 -0800842 Func.indent(4) << "} // case " << CurOp << "\n";
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000843 Func.indent(2) << "} // switch\n";
844 Func.indent(2) << "return false;\n}\n";
845
846 if (!MCOpPredicates.empty()) {
wangpc9d805ec2023-01-18 14:24:03 +0800847 o << "static bool " << ValidatorName << "(const MCOperand &MCOp,\n"
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000848 << " const MCSubtargetInfo &STI,\n"
849 << " unsigned PredicateIndex) {\n"
850 << " switch (PredicateIndex) {\n"
851 << " default:\n"
852 << " llvm_unreachable(\"Unknown MCOperandPredicate kind\");\n"
853 << " break;\n";
854
Ana Pazosead53f62019-12-16 15:09:48 -0800855 printPredicates(MCOpPredicates, "MCOperandPredicate", o);
856
857 o << " }\n"
858 << "}\n\n";
859 }
860
861 if (!ImmLeafPredicates.empty()) {
Zi Xuan Wucb380722021-11-18 10:22:21 +0800862 o << "static bool " << TargetName
Ana Pazosead53f62019-12-16 15:09:48 -0800863 << "ValidateMachineOperand(const MachineOperand &MO,\n"
Zi Xuan Wucb380722021-11-18 10:22:21 +0800864 << " const " << TargetName << "Subtarget *Subtarget,\n"
Ana Pazosead53f62019-12-16 15:09:48 -0800865 << " unsigned PredicateIndex) {\n"
Jay Foad94474cd2020-11-06 14:19:59 +0000866 << " int64_t Imm = MO.getImm();\n"
Ana Pazosead53f62019-12-16 15:09:48 -0800867 << " switch (PredicateIndex) {\n"
868 << " default:\n"
869 << " llvm_unreachable(\"Unknown ImmLeaf Predicate kind\");\n"
870 << " break;\n";
871
872 printPredicates(ImmLeafPredicates, "ImmediateCode", o);
873
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000874 o << " }\n"
875 << "}\n\n";
876 }
877
878 o << FuncH.str();
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000879 o << Func.str();
880
Ana Pazosead53f62019-12-16 15:09:48 -0800881 if (EType == EmitterType::Compress)
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000882 o << "\n#endif //GEN_COMPRESS_INSTR\n";
Ana Pazosead53f62019-12-16 15:09:48 -0800883 else if (EType == EmitterType::Uncompress)
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000884 o << "\n#endif //GEN_UNCOMPRESS_INSTR\n\n";
Ana Pazosead53f62019-12-16 15:09:48 -0800885 else if (EType == EmitterType::CheckCompress)
886 o << "\n#endif //GEN_CHECK_COMPRESS_INSTR\n\n";
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000887}
888
Zi Xuan Wucb380722021-11-18 10:22:21 +0800889void CompressInstEmitter::run(raw_ostream &o) {
Paul C. Anagnostopoulos8e7681b2020-10-13 12:40:45 -0400890 std::vector<Record *> Insts = Records.getAllDerivedDefinitions("CompressPat");
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000891
892 // Process the CompressPat definitions, validating them as we do so.
893 for (unsigned i = 0, e = Insts.size(); i != e; ++i)
894 evaluateCompressPat(Insts[i]);
895
896 // Emit file header.
897 emitSourceFileHeader("Compress instruction Source Fragment", o);
898 // Generate compressInst() function.
Ana Pazosead53f62019-12-16 15:09:48 -0800899 emitCompressInstEmitter(o, EmitterType::Compress);
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000900 // Generate uncompressInst() function.
Ana Pazosead53f62019-12-16 15:09:48 -0800901 emitCompressInstEmitter(o, EmitterType::Uncompress);
902 // Generate isCompressibleInst() function.
903 emitCompressInstEmitter(o, EmitterType::CheckCompress);
Sameer AbuAsalb881dd72018-04-06 21:07:05 +0000904}
905
NAKAMURA Takumi239c3d62023-02-19 14:30:14 +0900906static TableGen::Emitter::OptClass<CompressInstEmitter>
Craig Toppera84af4d2023-03-27 09:20:07 -0700907 X("gen-compress-inst-emitter", "Generate compressed instructions.");