commit 94474cd827eb0da56453e6419bd92e9e7b50eba4
author Jay Foad <jay.foad@amd.com> Fri Nov 06 14:19:59 2020 +0000
committer Copybara-Service <copybara-worker@google.com> Tue Nov 10 15:27:56 2020 -0800
tree eef927a6af38971fa75df1547164d090f9768ba4
parent e919272645adc9bdf139db76dbdaca9f8c25c334

[TableGen] Indentation and whitespace fixes in generated code. NFC.

Some of these were found by running clang-format over the generated
code, although that complains about far more issues than I have fixed
here.

Differential Revision: https://reviews.llvm.org/D90937

GitOrigin-RevId: d0b8810fe4ece12213936605b336777ed5fd06cc

utils/TableGen/RISCVCompressInstEmitter.cpp

diff --git a/utils/TableGen/RISCVCompressInstEmitter.cpp b/utils/TableGen/RISCVCompressInstEmitter.cpp
index b846441..2006442 100644
--- a/utils/TableGen/RISCVCompressInstEmitter.cpp
+++ b/utils/TableGen/RISCVCompressInstEmitter.cpp
@@ -37,11 +37,11 @@
 // compressing/uncompressing MCInst instructions, plus
 // some helper functions:
 //
-// bool compressInst(MCInst& OutInst, const MCInst &MI,
+// bool compressInst(MCInst &OutInst, const MCInst &MI,
 //                   const MCSubtargetInfo &STI,
 //                   MCContext &Context);
 //
-// bool uncompressInst(MCInst& OutInst, const MCInst &MI,
+// bool uncompressInst(MCInst &OutInst, const MCInst &MI,
 //                     const MCRegisterInfo &MRI,
 //                     const MCSubtargetInfo &STI);
 //
@@ -610,17 +610,17 @@
       << "#undef GEN_CHECK_COMPRESS_INSTR\n\n";
 
   if (EType == EmitterType::Compress) {
-    FuncH << "static bool compressInst(MCInst& OutInst,\n";
+    FuncH << "static bool compressInst(MCInst &OutInst,\n";
     FuncH.indent(25) << "const MCInst &MI,\n";
     FuncH.indent(25) << "const MCSubtargetInfo &STI,\n";
     FuncH.indent(25) << "MCContext &Context) {\n";
   } else if (EType == EmitterType::Uncompress){
-    FuncH << "static bool uncompressInst(MCInst& OutInst,\n";
+    FuncH << "static bool uncompressInst(MCInst &OutInst,\n";
     FuncH.indent(27) << "const MCInst &MI,\n";
     FuncH.indent(27) << "const MCRegisterInfo &MRI,\n";
     FuncH.indent(27) << "const MCSubtargetInfo &STI) {\n";
   } else if (EType == EmitterType::CheckCompress) {
-    FuncH << "static bool isCompressibleInst(const MachineInstr& MI,\n";
+    FuncH << "static bool isCompressibleInst(const MachineInstr &MI,\n";
     FuncH.indent(27) << "const RISCVSubtarget *Subtarget,\n";
     FuncH.indent(27) << "const MCRegisterInfo &MRI,\n";
     FuncH.indent(27) << "const MCSubtargetInfo &STI) {\n";
@@ -781,7 +781,7 @@
             unsigned Entry = getPredicates(ImmLeafPredicateMap, ImmLeafPredicates,
               DestOperand.Rec, StringRef("ImmediateCode"));
             CondStream.indent(6) << "MI.getOperand(" + std::to_string(OpIdx) +
-                                    ").isImm() && \n";
+                                    ").isImm() &&\n";
             CondStream.indent(6) << Namespace + "ValidateMachineOperand(" +
                                         "MI.getOperand(" + std::to_string(OpIdx) +
                                         "), Subtarget, " + std::to_string(Entry) +
@@ -858,7 +858,7 @@
       << "ValidateMachineOperand(const MachineOperand &MO,\n"
       << "                  const RISCVSubtarget *Subtarget,\n"
       << "                  unsigned PredicateIndex) {\n"
-      << "  int64_t Imm = MO.getImm(); \n"
+      << "  int64_t Imm = MO.getImm();\n"
       << "  switch (PredicateIndex) {\n"
       << "  default:\n"
       << "    llvm_unreachable(\"Unknown ImmLeaf Predicate kind\");\n"