blob: 2a976be5ef0c26727a844781990b4e66406f99da [file] [edit]
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../Inputs/zfhmin.s | FileCheck %s
# CHECK: Resources:
# CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3
# CHECK-NEXT: [1] - SiFiveP600Div:1
# CHECK-NEXT: [2] - SiFiveP600FEXQ0:1
# CHECK-NEXT: [3] - SiFiveP600FEXQ1:1
# CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1
# CHECK-NEXT: [5] - SiFiveP600FloatDiv:1
# CHECK-NEXT: [6] - SiFiveP600IEXQ0:1
# CHECK-NEXT: [7] - SiFiveP600IEXQ1:1
# CHECK-NEXT: [8] - SiFiveP600IEXQ2:1
# CHECK-NEXT: [9] - SiFiveP600IEXQ3:1
# CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3
# CHECK-NEXT: [11] - SiFiveP600LDST:2
# CHECK-NEXT: [12] - SiFiveP600VDiv:1
# CHECK-NEXT: [13] - SiFiveP600VEXQ0:1
# CHECK-NEXT: [14] - SiFiveP600VEXQ1:1
# CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1
# CHECK-NEXT: [16] - SiFiveP600VLD:1
# CHECK-NEXT: [17] - SiFiveP600VST:1
# CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK-NEXT: [7]: Bypass Latency
# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
# CHECK-NEXT: [9]: LLVM Opcode Name
# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
# CHECK-NEXT: 1 5 0.50 * 5 SiFiveP600LDST FLH flh ft0, 0(a0)
# CHECK-NEXT: 1 1 0.50 * 1 SiFiveP600LDST FSH fsh ft0, 0(a0)
# CHECK-NEXT: 1 2 1.00 2 SiFiveP600FEXQ0,SiFiveP600FloatArith FMV_X_H fmv.x.h a2, fs7
# CHECK-NEXT: 1 2 1.00 2 SiFiveP600IEXQ1,SiFiveP600IntArith FMV_H_X fmv.h.x ft1, a6
# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FCVT_S_H fcvt.s.h fa0, ft0
# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FCVT_S_H fcvt.s.h fa0, ft0, rup
# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FCVT_H_S fcvt.h.s ft2, fa2
# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FCVT_D_H fcvt.d.h fa0, ft0
# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FCVT_D_H fcvt.d.h fa0, ft0, rup
# CHECK-NEXT: 1 2 0.50 2 SiFiveP600FloatArith FCVT_H_D fcvt.h.d ft2, fa2
# CHECK: Resources:
# CHECK-NEXT: [0] - SiFiveP600Div
# CHECK-NEXT: [1] - SiFiveP600FEXQ0
# CHECK-NEXT: [2] - SiFiveP600FEXQ1
# CHECK-NEXT: [3] - SiFiveP600FloatDiv
# CHECK-NEXT: [4] - SiFiveP600IEXQ0
# CHECK-NEXT: [5] - SiFiveP600IEXQ1
# CHECK-NEXT: [6] - SiFiveP600IEXQ2
# CHECK-NEXT: [7] - SiFiveP600IEXQ3
# CHECK-NEXT: [8.0] - SiFiveP600LDST
# CHECK-NEXT: [8.1] - SiFiveP600LDST
# CHECK-NEXT: [9] - SiFiveP600VDiv
# CHECK-NEXT: [10] - SiFiveP600VEXQ0
# CHECK-NEXT: [11] - SiFiveP600VEXQ1
# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
# CHECK-NEXT: [13] - SiFiveP600VLD
# CHECK-NEXT: [14] - SiFiveP600VST
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
# CHECK-NEXT: - 4.00 3.00 - - 1.00 - - 1.00 1.00 - - - - - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - flh ft0, 0(a0)
# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - fsh ft0, 0(a0)
# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - fmv.x.h a2, fs7
# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - fmv.h.x ft1, a6
# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fcvt.s.h fa0, ft0
# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fcvt.s.h fa0, ft0, rup
# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fcvt.h.s ft2, fa2
# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fcvt.d.h fa0, ft0
# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fcvt.d.h fa0, ft0, rup
# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - fcvt.h.d ft2, fa2