| # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py |
| # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 -instruction-tables=full %p/../Inputs/integer.s | FileCheck %s |
| |
| # CHECK: Resources: |
| # CHECK-NEXT: [0] - SiFiveP600Branch:2 SiFiveP600IEXQ2, SiFiveP600IEXQ3 |
| # CHECK-NEXT: [1] - SiFiveP600Div:1 |
| # CHECK-NEXT: [2] - SiFiveP600FEXQ0:1 |
| # CHECK-NEXT: [3] - SiFiveP600FEXQ1:1 |
| # CHECK-NEXT: [4] - SiFiveP600FloatArith:2 SiFiveP600FEXQ0, SiFiveP600FEXQ1 |
| # CHECK-NEXT: [5] - SiFiveP600FloatDiv:1 |
| # CHECK-NEXT: [6] - SiFiveP600IEXQ0:1 |
| # CHECK-NEXT: [7] - SiFiveP600IEXQ1:1 |
| # CHECK-NEXT: [8] - SiFiveP600IEXQ2:1 |
| # CHECK-NEXT: [9] - SiFiveP600IEXQ3:1 |
| # CHECK-NEXT: [10] - SiFiveP600IntArith:4 SiFiveP600IEXQ0, SiFiveP600IEXQ1, SiFiveP600IEXQ2, SiFiveP600IEXQ3 |
| # CHECK-NEXT: [11] - SiFiveP600LDST:2 |
| # CHECK-NEXT: [12] - SiFiveP600VDiv:1 |
| # CHECK-NEXT: [13] - SiFiveP600VEXQ0:1 |
| # CHECK-NEXT: [14] - SiFiveP600VEXQ1:1 |
| # CHECK-NEXT: [15] - SiFiveP600VFloatDiv:1 |
| # CHECK-NEXT: [16] - SiFiveP600VLD:1 |
| # CHECK-NEXT: [17] - SiFiveP600VST:1 |
| # CHECK-NEXT: [18] - SiFiveP600VectorArith:2 SiFiveP600VEXQ0, SiFiveP600VEXQ1 |
| |
| # CHECK: Instruction Info: |
| # CHECK-NEXT: [1]: #uOps |
| # CHECK-NEXT: [2]: Latency |
| # CHECK-NEXT: [3]: RThroughput |
| # CHECK-NEXT: [4]: MayLoad |
| # CHECK-NEXT: [5]: MayStore |
| # CHECK-NEXT: [6]: HasSideEffects (U) |
| # CHECK-NEXT: [7]: Bypass Latency |
| # CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle]) |
| # CHECK-NEXT: [9]: LLVM Opcode Name |
| |
| # CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_ADDI addi a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_ADDIW addiw a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SLTI slti a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SLTIU seqz a0, a0 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_ANDI andi a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith ORI ori a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith XORI xori a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_SLLI slli a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_SRLI srli a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_SRAI srai a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SLLIW slliw a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SRLIW srliw a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SRAIW sraiw a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_LUI lui a0, 1 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith AUIPC auipc a1, 1 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_ADD add a0, a0, a1 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_ADDW addw a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SLT slt a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SLTU sltu a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_AND and a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_OR or a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_XOR xor a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SLL sll a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SRL srl a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SRA sra a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SLLW sllw a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SRLW srlw a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith SRAW sraw a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_SUB sub a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_SUBW subw a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.50 1 SiFiveP600Branch,SiFiveP600IntArith JAL jal a0, .Ltmp0 |
| # CHECK-NEXT: 1 1 0.50 1 SiFiveP600Branch,SiFiveP600IntArith C_JALR jalr a0 |
| # CHECK-NEXT: 1 1 0.50 1 SiFiveP600Branch,SiFiveP600IntArith BEQ beq a0, a0, .Ltmp1 |
| # CHECK-NEXT: 1 1 0.50 1 SiFiveP600Branch,SiFiveP600IntArith BNE bne a0, a0, .Ltmp2 |
| # CHECK-NEXT: 1 1 0.50 1 SiFiveP600Branch,SiFiveP600IntArith BLT blt a0, a0, .Ltmp3 |
| # CHECK-NEXT: 1 1 0.50 1 SiFiveP600Branch,SiFiveP600IntArith BLTU bltu a0, a0, .Ltmp4 |
| # CHECK-NEXT: 1 1 0.50 1 SiFiveP600Branch,SiFiveP600IntArith BGE bge a0, a0, .Ltmp5 |
| # CHECK-NEXT: 1 1 0.50 1 SiFiveP600Branch,SiFiveP600IntArith BGEU bgeu a0, a0, .Ltmp6 |
| # CHECK-NEXT: 1 1 0.25 1 SiFiveP600IntArith C_ADD add a0, a0, a0 |
| # CHECK-NEXT: 1 4 0.50 * 4 SiFiveP600LDST LB lb t0, 0(a0) |
| # CHECK-NEXT: 1 4 0.50 * 4 SiFiveP600LDST LBU lbu t0, 0(a0) |
| # CHECK-NEXT: 1 4 0.50 * 4 SiFiveP600LDST LH lh t0, 0(a0) |
| # CHECK-NEXT: 1 4 0.50 * 4 SiFiveP600LDST LHU lhu t0, 0(a0) |
| # CHECK-NEXT: 1 4 0.50 * 4 SiFiveP600LDST LW lw t0, 0(a0) |
| # CHECK-NEXT: 1 4 0.50 * 4 SiFiveP600LDST LWU lwu t0, 0(a0) |
| # CHECK-NEXT: 1 4 0.50 * 4 SiFiveP600LDST LD ld t0, 0(a0) |
| # CHECK-NEXT: 1 1 0.50 * 1 SiFiveP600LDST SB sb t0, 0(a0) |
| # CHECK-NEXT: 1 1 0.50 * 1 SiFiveP600LDST SH sh t0, 0(a0) |
| # CHECK-NEXT: 1 1 0.50 * 1 SiFiveP600LDST SW sw t0, 0(a0) |
| # CHECK-NEXT: 1 1 0.50 * 1 SiFiveP600LDST SD sd t0, 0(a0) |
| # CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith CSRRW csrrw t0, 4095, t1 |
| # CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith CSRRS csrrs s3, fflags, s5 |
| # CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith CSRRC csrrc sp, 0, ra |
| # CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith CSRRWI csrrwi a5, 0, 0 |
| # CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith CSRRSI csrrsi t2, 4095, 31 |
| # CHECK-NEXT: 1 1 1.00 U 1 SiFiveP600IEXQ0,SiFiveP600IntArith CSRRCI csrrci t1, sscratch, 5 |
| |
| # CHECK: Resources: |
| # CHECK-NEXT: [0] - SiFiveP600Div |
| # CHECK-NEXT: [1] - SiFiveP600FEXQ0 |
| # CHECK-NEXT: [2] - SiFiveP600FEXQ1 |
| # CHECK-NEXT: [3] - SiFiveP600FloatDiv |
| # CHECK-NEXT: [4] - SiFiveP600IEXQ0 |
| # CHECK-NEXT: [5] - SiFiveP600IEXQ1 |
| # CHECK-NEXT: [6] - SiFiveP600IEXQ2 |
| # CHECK-NEXT: [7] - SiFiveP600IEXQ3 |
| # CHECK-NEXT: [8.0] - SiFiveP600LDST |
| # CHECK-NEXT: [8.1] - SiFiveP600LDST |
| # CHECK-NEXT: [9] - SiFiveP600VDiv |
| # CHECK-NEXT: [10] - SiFiveP600VEXQ0 |
| # CHECK-NEXT: [11] - SiFiveP600VEXQ1 |
| # CHECK-NEXT: [12] - SiFiveP600VFloatDiv |
| # CHECK-NEXT: [13] - SiFiveP600VLD |
| # CHECK-NEXT: [14] - SiFiveP600VST |
| |
| # CHECK: Resource pressure per iteration: |
| # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] |
| # CHECK-NEXT: - - - - 13.75 7.75 11.75 11.75 5.50 5.50 - - - - - - |
| |
| # CHECK: Resource pressure by instruction: |
| # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions: |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - addi a0, a0, 1 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - addiw a0, a0, 1 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - slti a0, a0, 1 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - seqz a0, a0 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - andi a0, a0, 1 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - ori a0, a0, 1 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - xori a0, a0, 1 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - slli a0, a0, 1 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - srli a0, a0, 1 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - srai a0, a0, 1 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - slliw a0, a0, 1 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - srliw a0, a0, 1 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sraiw a0, a0, 1 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - lui a0, 1 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - auipc a1, 1 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - add a0, a0, a1 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - addw a0, a0, a0 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - slt a0, a0, a0 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sltu a0, a0, a0 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - and a0, a0, a0 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - or a0, a0, a0 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - xor a0, a0, a0 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sll a0, a0, a0 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - srl a0, a0, a0 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sra a0, a0, a0 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sllw a0, a0, a0 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - srlw a0, a0, a0 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sraw a0, a0, a0 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sub a0, a0, a0 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - subw a0, a0, a0 |
| # CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - jal a0, .Ltmp0 |
| # CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - jalr a0 |
| # CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - beq a0, a0, .Ltmp1 |
| # CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - bne a0, a0, .Ltmp2 |
| # CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - blt a0, a0, .Ltmp3 |
| # CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - bltu a0, a0, .Ltmp4 |
| # CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - bge a0, a0, .Ltmp5 |
| # CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - bgeu a0, a0, .Ltmp6 |
| # CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - add a0, a0, a0 |
| # CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - lb t0, 0(a0) |
| # CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - lbu t0, 0(a0) |
| # CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - lh t0, 0(a0) |
| # CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - lhu t0, 0(a0) |
| # CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - lw t0, 0(a0) |
| # CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - lwu t0, 0(a0) |
| # CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - ld t0, 0(a0) |
| # CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - sb t0, 0(a0) |
| # CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - sh t0, 0(a0) |
| # CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - sw t0, 0(a0) |
| # CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - sd t0, 0(a0) |
| # CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - csrrw t0, 4095, t1 |
| # CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - csrrs s3, fflags, s5 |
| # CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - csrrc sp, 0, ra |
| # CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - csrrwi a5, 0, 0 |
| # CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - csrrsi t2, 4095, 31 |
| # CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - csrrci t1, sscratch, 5 |
