| # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py |
| # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 -instruction-tables=full %p/../Inputs/integer.s | FileCheck %s |
| |
| # CHECK: Resources: |
| # CHECK-NEXT: [0] - SiFiveP400Div:1 |
| # CHECK-NEXT: [1] - SiFiveP400FEXQ0:1 |
| # CHECK-NEXT: [2] - SiFiveP400FloatDiv:1 |
| # CHECK-NEXT: [3] - SiFiveP400IEXQ0:1 |
| # CHECK-NEXT: [4] - SiFiveP400IEXQ1:1 |
| # CHECK-NEXT: [5] - SiFiveP400IEXQ2:1 |
| # CHECK-NEXT: [6] - SiFiveP400IntArith:3 SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2 |
| # CHECK-NEXT: [7] - SiFiveP400Load:1 |
| # CHECK-NEXT: [8] - SiFiveP400Store:1 |
| # CHECK-NEXT: [9] - SiFiveP400VDiv:1 |
| # CHECK-NEXT: [10] - SiFiveP400VEXQ0:1 |
| # CHECK-NEXT: [11] - SiFiveP400VFloatDiv:1 |
| # CHECK-NEXT: [12] - SiFiveP400VLD:1 |
| # CHECK-NEXT: [13] - SiFiveP400VST:1 |
| |
| # CHECK: Instruction Info: |
| # CHECK-NEXT: [1]: #uOps |
| # CHECK-NEXT: [2]: Latency |
| # CHECK-NEXT: [3]: RThroughput |
| # CHECK-NEXT: [4]: MayLoad |
| # CHECK-NEXT: [5]: MayStore |
| # CHECK-NEXT: [6]: HasSideEffects (U) |
| # CHECK-NEXT: [7]: Bypass Latency |
| # CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle]) |
| # CHECK-NEXT: [9]: LLVM Opcode Name |
| |
| # CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_ADDI addi a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_ADDIW addiw a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SLTI slti a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SLTIU seqz a0, a0 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_ANDI andi a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith ORI ori a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith XORI xori a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_SLLI slli a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_SRLI srli a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_SRAI srai a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SLLIW slliw a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SRLIW srliw a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SRAIW sraiw a0, a0, 1 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_LUI lui a0, 1 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith AUIPC auipc a1, 1 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_ADD add a0, a0, a1 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_ADDW addw a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SLT slt a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SLTU sltu a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_AND and a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_OR or a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_XOR xor a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SLL sll a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SRL srl a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SRA sra a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SLLW sllw a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SRLW srlw a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith SRAW sraw a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_SUB sub a0, a0, a0 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_SUBW subw a0, a0, a0 |
| # CHECK-NEXT: 1 1 1.00 1 SiFiveP400IEXQ0,SiFiveP400IntArith JAL jal a0, .Ltmp0 |
| # CHECK-NEXT: 1 1 1.00 1 SiFiveP400IEXQ0,SiFiveP400IntArith C_JALR jalr a0 |
| # CHECK-NEXT: 1 1 1.00 1 SiFiveP400IEXQ0,SiFiveP400IntArith BEQ beq a0, a0, .Ltmp1 |
| # CHECK-NEXT: 1 1 1.00 1 SiFiveP400IEXQ0,SiFiveP400IntArith BNE bne a0, a0, .Ltmp2 |
| # CHECK-NEXT: 1 1 1.00 1 SiFiveP400IEXQ0,SiFiveP400IntArith BLT blt a0, a0, .Ltmp3 |
| # CHECK-NEXT: 1 1 1.00 1 SiFiveP400IEXQ0,SiFiveP400IntArith BLTU bltu a0, a0, .Ltmp4 |
| # CHECK-NEXT: 1 1 1.00 1 SiFiveP400IEXQ0,SiFiveP400IntArith BGE bge a0, a0, .Ltmp5 |
| # CHECK-NEXT: 1 1 1.00 1 SiFiveP400IEXQ0,SiFiveP400IntArith BGEU bgeu a0, a0, .Ltmp6 |
| # CHECK-NEXT: 1 1 0.33 1 SiFiveP400IntArith C_ADD add a0, a0, a0 |
| # CHECK-NEXT: 1 4 1.00 * 4 SiFiveP400Load LB lb t0, 0(a0) |
| # CHECK-NEXT: 1 4 1.00 * 4 SiFiveP400Load LBU lbu t0, 0(a0) |
| # CHECK-NEXT: 1 4 1.00 * 4 SiFiveP400Load LH lh t0, 0(a0) |
| # CHECK-NEXT: 1 4 1.00 * 4 SiFiveP400Load LHU lhu t0, 0(a0) |
| # CHECK-NEXT: 1 4 1.00 * 4 SiFiveP400Load LW lw t0, 0(a0) |
| # CHECK-NEXT: 1 4 1.00 * 4 SiFiveP400Load LWU lwu t0, 0(a0) |
| # CHECK-NEXT: 1 4 1.00 * 4 SiFiveP400Load LD ld t0, 0(a0) |
| # CHECK-NEXT: 1 1 1.00 * 1 SiFiveP400Store SB sb t0, 0(a0) |
| # CHECK-NEXT: 1 1 1.00 * 1 SiFiveP400Store SH sh t0, 0(a0) |
| # CHECK-NEXT: 1 1 1.00 * 1 SiFiveP400Store SW sw t0, 0(a0) |
| # CHECK-NEXT: 1 1 1.00 * 1 SiFiveP400Store SD sd t0, 0(a0) |
| # CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith CSRRW csrrw t0, 4095, t1 |
| # CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith CSRRS csrrs s3, fflags, s5 |
| # CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith CSRRC csrrc sp, 0, ra |
| # CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith CSRRWI csrrwi a5, 0, 0 |
| # CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith CSRRSI csrrsi t2, 4095, 31 |
| # CHECK-NEXT: 1 1 1.00 U 1 SiFiveP400IEXQ1,SiFiveP400IntArith CSRRCI csrrci t1, sscratch, 5 |
| |
| # CHECK: Resources: |
| # CHECK-NEXT: [0] - SiFiveP400Div |
| # CHECK-NEXT: [1] - SiFiveP400FEXQ0 |
| # CHECK-NEXT: [2] - SiFiveP400FloatDiv |
| # CHECK-NEXT: [3] - SiFiveP400IEXQ0 |
| # CHECK-NEXT: [4] - SiFiveP400IEXQ1 |
| # CHECK-NEXT: [5] - SiFiveP400IEXQ2 |
| # CHECK-NEXT: [6] - SiFiveP400Load |
| # CHECK-NEXT: [7] - SiFiveP400Store |
| # CHECK-NEXT: [8] - SiFiveP400VDiv |
| # CHECK-NEXT: [9] - SiFiveP400VEXQ0 |
| # CHECK-NEXT: [10] - SiFiveP400VFloatDiv |
| # CHECK-NEXT: [11] - SiFiveP400VLD |
| # CHECK-NEXT: [12] - SiFiveP400VST |
| |
| # CHECK: Resource pressure per iteration: |
| # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] |
| # CHECK-NEXT: - - - 18.33 16.33 10.33 7.00 4.00 - - - - - |
| |
| # CHECK: Resource pressure by instruction: |
| # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions: |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - addi a0, a0, 1 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - addiw a0, a0, 1 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - slti a0, a0, 1 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - seqz a0, a0 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - andi a0, a0, 1 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - ori a0, a0, 1 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - xori a0, a0, 1 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - slli a0, a0, 1 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - srli a0, a0, 1 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - srai a0, a0, 1 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - slliw a0, a0, 1 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - srliw a0, a0, 1 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sraiw a0, a0, 1 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - lui a0, 1 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - auipc a1, 1 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - add a0, a0, a1 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - addw a0, a0, a0 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - slt a0, a0, a0 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sltu a0, a0, a0 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - and a0, a0, a0 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - or a0, a0, a0 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - xor a0, a0, a0 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sll a0, a0, a0 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - srl a0, a0, a0 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sra a0, a0, a0 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sllw a0, a0, a0 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - srlw a0, a0, a0 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sraw a0, a0, a0 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - sub a0, a0, a0 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - subw a0, a0, a0 |
| # CHECK-NEXT: - - - 1.00 - - - - - - - - - jal a0, .Ltmp0 |
| # CHECK-NEXT: - - - 1.00 - - - - - - - - - jalr a0 |
| # CHECK-NEXT: - - - 1.00 - - - - - - - - - beq a0, a0, .Ltmp1 |
| # CHECK-NEXT: - - - 1.00 - - - - - - - - - bne a0, a0, .Ltmp2 |
| # CHECK-NEXT: - - - 1.00 - - - - - - - - - blt a0, a0, .Ltmp3 |
| # CHECK-NEXT: - - - 1.00 - - - - - - - - - bltu a0, a0, .Ltmp4 |
| # CHECK-NEXT: - - - 1.00 - - - - - - - - - bge a0, a0, .Ltmp5 |
| # CHECK-NEXT: - - - 1.00 - - - - - - - - - bgeu a0, a0, .Ltmp6 |
| # CHECK-NEXT: - - - 0.33 0.33 0.33 - - - - - - - add a0, a0, a0 |
| # CHECK-NEXT: - - - - - - 1.00 - - - - - - lb t0, 0(a0) |
| # CHECK-NEXT: - - - - - - 1.00 - - - - - - lbu t0, 0(a0) |
| # CHECK-NEXT: - - - - - - 1.00 - - - - - - lh t0, 0(a0) |
| # CHECK-NEXT: - - - - - - 1.00 - - - - - - lhu t0, 0(a0) |
| # CHECK-NEXT: - - - - - - 1.00 - - - - - - lw t0, 0(a0) |
| # CHECK-NEXT: - - - - - - 1.00 - - - - - - lwu t0, 0(a0) |
| # CHECK-NEXT: - - - - - - 1.00 - - - - - - ld t0, 0(a0) |
| # CHECK-NEXT: - - - - - - - 1.00 - - - - - sb t0, 0(a0) |
| # CHECK-NEXT: - - - - - - - 1.00 - - - - - sh t0, 0(a0) |
| # CHECK-NEXT: - - - - - - - 1.00 - - - - - sw t0, 0(a0) |
| # CHECK-NEXT: - - - - - - - 1.00 - - - - - sd t0, 0(a0) |
| # CHECK-NEXT: - - - - 1.00 - - - - - - - - csrrw t0, 4095, t1 |
| # CHECK-NEXT: - - - - 1.00 - - - - - - - - csrrs s3, fflags, s5 |
| # CHECK-NEXT: - - - - 1.00 - - - - - - - - csrrc sp, 0, ra |
| # CHECK-NEXT: - - - - 1.00 - - - - - - - - csrrwi a5, 0, 0 |
| # CHECK-NEXT: - - - - 1.00 - - - - - - - - csrrsi t2, 4095, 31 |
| # CHECK-NEXT: - - - - 1.00 - - - - - - - - csrrci t1, sscratch, 5 |
