test/Transforms/SLPVectorizer/volatile-loads-reduction.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt < %s -passes=slp-vectorizer -S | FileCheck %s

@a = external global i32

; The reduction of the volatile loads must not be vectorized.
define i32 @volatile_loads_reduction(i32 %a) {
; CHECK-LABEL: define i32 @volatile_loads_reduction(
; CHECK-SAME: i32 [[A:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[A1:%.*]] = load volatile i32, ptr @a, align 4
; CHECK-NEXT:    [[A2:%.*]] = load volatile i32, ptr @a, align 4
; CHECK-NEXT:    [[A3:%.*]] = load volatile i32, ptr @a, align 4
; CHECK-NEXT:    [[A4:%.*]] = load volatile i32, ptr @a, align 4
; CHECK-NEXT:    [[A5:%.*]] = load volatile i32, ptr @a, align 4
; CHECK-NEXT:    [[A6:%.*]] = load volatile i32, ptr @a, align 4
; CHECK-NEXT:    [[A7:%.*]] = load volatile i32, ptr @a, align 4
; CHECK-NEXT:    [[A8:%.*]] = load volatile i32, ptr @a, align 4
; CHECK-NEXT:    [[A9:%.*]] = load volatile i32, ptr @a, align 4
; CHECK-NEXT:    [[A10:%.*]] = load volatile i32, ptr @a, align 4
; CHECK-NEXT:    [[A11:%.*]] = load volatile i32, ptr @a, align 4
; CHECK-NEXT:    [[A12:%.*]] = load volatile i32, ptr @a, align 4
; CHECK-NEXT:    [[TMP0:%.*]] = mul i32 [[A6]], 2
; CHECK-NEXT:    [[TMP1:%.*]] = mul i32 [[A1]], 2
; CHECK-NEXT:    [[OP_RDX:%.*]] = add i32 [[TMP0]], [[TMP1]]
; CHECK-NEXT:    [[OP_RDX1:%.*]] = add i32 [[OP_RDX]], [[A]]
; CHECK-NEXT:    [[OP_RDX2:%.*]] = add i32 [[A12]], [[A11]]
; CHECK-NEXT:    [[OP_RDX3:%.*]] = add i32 [[A10]], [[A9]]
; CHECK-NEXT:    [[OP_RDX4:%.*]] = add i32 [[A8]], [[A5]]
; CHECK-NEXT:    [[OP_RDX5:%.*]] = add i32 [[A4]], [[A3]]
; CHECK-NEXT:    [[OP_RDX6:%.*]] = add i32 [[OP_RDX1]], [[OP_RDX2]]
; CHECK-NEXT:    [[OP_RDX7:%.*]] = add i32 [[OP_RDX3]], [[OP_RDX4]]
; CHECK-NEXT:    [[OP_RDX8:%.*]] = add i32 [[OP_RDX5]], [[A2]]
; CHECK-NEXT:    [[OP_RDX9:%.*]] = add i32 [[OP_RDX6]], [[OP_RDX7]]
; CHECK-NEXT:    [[OP_RDX10:%.*]] = add i32 [[OP_RDX9]], [[OP_RDX8]]
; CHECK-NEXT:    ret i32 [[OP_RDX10]]
;
entry:
  %a1 = load volatile i32, ptr @a
  %x1 = add i32 %a1,  %a1
  %a2 = load volatile i32, ptr @a
  %x2 = add i32 %x1, %a2
  %a3 = load volatile i32, ptr @a
  %x3 = add i32 %x2, %a3
  %a4 = load volatile i32, ptr @a
  %x4 = add i32 %x3, %a4
  %a5 = load volatile i32, ptr @a
  %x5 = add i32 %x4, %a5
  %a6 = load volatile i32, ptr @a
  %x6 = add i32 %x5, %a6
  %a7 = load volatile i32, ptr @a
  %x7 = add i32 %x6, %a6
  %a8 = load volatile i32, ptr @a
  %x8 = add i32 %x7, %a8
  %a9 = load volatile i32, ptr @a
  %x9 = add i32 %x8, %a9
  %a10 = load volatile i32, ptr @a
  %x10 = add i32 %x9, %a10
  %a11 = load volatile i32, ptr @a
  %x11 = add i32 %x10, %a11
  %a12 = load volatile i32, ptr @a
  %x12 = add i32 %x11, %a12
  %add = add i32 %x12, %a
  ret i32 %add
}