test/Transforms/SLPVectorizer/X86/bswap-reduction-aliased.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s

define i32 @test(ptr %x, ptr %y) {
; CHECK-LABEL: define i32 @test(
; CHECK-SAME: ptr [[X:%.*]], ptr [[Y:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[X]], align 1
; CHECK-NEXT:    [[OR10:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP0]])
; CHECK-NEXT:    store i8 1, ptr [[Y]], align 1
; CHECK-NEXT:    ret i32 [[OR10]]
;
entry:
  %0 = load i8, ptr %x, align 1
  %arrayidx1 = getelementptr inbounds nuw i8, ptr %x, i64 1
  %1 = load i8, ptr %arrayidx1, align 1
  %arrayidx2 = getelementptr inbounds nuw i8, ptr %x, i64 2
  %2 = load i8, ptr %arrayidx2, align 1
  %arrayidx3 = getelementptr inbounds nuw i8, ptr %x, i64 3
  %3 = load i8, ptr %arrayidx3, align 1
  store i8 1, ptr %y, align 1
  %conv = zext i8 %3 to i32
  %conv4 = zext i8 %2 to i32
  %shl = shl nuw nsw i32 %conv4, 8
  %conv5 = zext i8 %1 to i32
  %shl6 = shl nuw nsw i32 %conv5, 16
  %conv8 = zext i8 %0 to i32
  %shl9 = shl nuw i32 %conv8, 24
  %or = or disjoint i32 %shl6, %shl9
  %or7 = or disjoint i32 %or, %conv
  %or10 = or disjoint i32 %or7, %shl
  ret i32 %or10
}