test/Transforms/LoopVectorize/runtime-checks-sibling-loop-addrec.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s

; Tests for runtime checks where the pointer bounds contain an AddRec of an
; earlier sibling loop.

define void @bound_is_ptr_iv_of_sibling_loop(ptr %a, ptr %b, i64 %n, i64 %m) {
; CHECK-LABEL: define void @bound_is_ptr_iv_of_sibling_loop(
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]], i64 [[M:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*]]:
; CHECK-NEXT:    [[B1:%.*]] = ptrtoaddr ptr [[B]] to i64
; CHECK-NEXT:    br label %[[LOOP_1:.*]]
; CHECK:       [[LOOP_1]]:
; CHECK-NEXT:    [[PTR_IV:%.*]] = phi ptr [ [[B]], %[[ENTRY]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_1]] ]
; CHECK-NEXT:    [[IV_1:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP_1]] ]
; CHECK-NEXT:    call void @use(i64 [[IV_1]])
; CHECK-NEXT:    [[PTR_IV_NEXT]] = getelementptr inbounds i8, ptr [[PTR_IV]], i64 12
; CHECK-NEXT:    [[IV_1_NEXT]] = add nuw i64 [[IV_1]], 1
; CHECK-NEXT:    [[EC_1:%.*]] = icmp ugt i64 [[IV_1]], [[M]]
; CHECK-NEXT:    br i1 [[EC_1]], label %[[PH_2:.*]], label %[[LOOP_1]]
; CHECK:       [[PH_2]]:
; CHECK-NEXT:    [[PTR_IV_LCSSA:%.*]] = phi ptr [ [[PTR_IV]], %[[LOOP_1]] ]
; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4
; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
; CHECK:       [[VECTOR_MEMCHECK]]:
; CHECK-NEXT:    [[TMP0:%.*]] = shl i64 [[N]], 2
; CHECK-NEXT:    [[TMP1:%.*]] = sub i64 0, [[B1]]
; CHECK-NEXT:    [[TMP2:%.*]] = ptrtoaddr ptr [[PTR_IV_LCSSA]] to i64
; CHECK-NEXT:    [[TMP3:%.*]] = add i64 [[TMP2]], [[TMP1]]
; CHECK-NEXT:    [[TMP4:%.*]] = add i64 [[TMP0]], [[TMP3]]
; CHECK-NEXT:    [[SCEVGEP:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP5:%.*]] = shl i64 [[N]], 3
; CHECK-NEXT:    [[TMP6:%.*]] = add i64 [[TMP5]], -4
; CHECK-NEXT:    [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP6]]
; CHECK-NEXT:    [[BOUND0:%.*]] = icmp ult ptr [[PTR_IV_LCSSA]], [[SCEVGEP2]]
; CHECK-NEXT:    [[BOUND1:%.*]] = icmp ult ptr [[A]], [[SCEVGEP]]
; CHECK-NEXT:    [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
; CHECK-NEXT:    br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
; CHECK:       [[VECTOR_PH]]:
; CHECK-NEXT:    [[TMP7:%.*]] = and i64 [[N]], 3
; CHECK-NEXT:    [[N_VEC:%.*]] = sub i64 [[N]], [[TMP7]]
; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
; CHECK:       [[VECTOR_BODY]]:
; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT:    [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT:    [[TMP8:%.*]] = shl nuw nsw <4 x i64> [[VEC_IND]], splat (i64 1)
; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <4 x i64> [[TMP8]], i64 0
; CHECK-NEXT:    [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP9]]
; CHECK-NEXT:    [[TMP11:%.*]] = extractelement <4 x i64> [[TMP8]], i64 1
; CHECK-NEXT:    [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP11]]
; CHECK-NEXT:    [[TMP13:%.*]] = extractelement <4 x i64> [[TMP8]], i64 2
; CHECK-NEXT:    [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP13]]
; CHECK-NEXT:    [[TMP15:%.*]] = extractelement <4 x i64> [[TMP8]], i64 3
; CHECK-NEXT:    [[TMP16:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP15]]
; CHECK-NEXT:    [[TMP17:%.*]] = load i32, ptr [[TMP10]], align 4, !alias.scope [[META0:![0-9]+]]
; CHECK-NEXT:    [[TMP18:%.*]] = load i32, ptr [[TMP12]], align 4, !alias.scope [[META0]]
; CHECK-NEXT:    [[TMP19:%.*]] = load i32, ptr [[TMP14]], align 4, !alias.scope [[META0]]
; CHECK-NEXT:    [[TMP20:%.*]] = load i32, ptr [[TMP16]], align 4, !alias.scope [[META0]]
; CHECK-NEXT:    [[TMP21:%.*]] = insertelement <4 x i32> poison, i32 [[TMP17]], i64 0
; CHECK-NEXT:    [[TMP22:%.*]] = insertelement <4 x i32> [[TMP21]], i32 [[TMP18]], i64 1
; CHECK-NEXT:    [[TMP23:%.*]] = insertelement <4 x i32> [[TMP22]], i32 [[TMP19]], i64 2
; CHECK-NEXT:    [[TMP24:%.*]] = insertelement <4 x i32> [[TMP23]], i32 [[TMP20]], i64 3
; CHECK-NEXT:    [[TMP25:%.*]] = getelementptr inbounds i32, ptr [[PTR_IV_LCSSA]], i64 [[INDEX]]
; CHECK-NEXT:    store <4 x i32> [[TMP24]], ptr [[TMP25]], align 4, !alias.scope [[META3:![0-9]+]], !noalias [[META0]]
; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT:    [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4)
; CHECK-NEXT:    [[TMP26:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT:    br i1 [[TMP26]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK:       [[MIDDLE_BLOCK]]:
; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; CHECK-NEXT:    br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK:       [[SCALAR_PH]]:
; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[PH_2]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
; CHECK-NEXT:    br label %[[LOOP_2:.*]]
; CHECK:       [[LOOP_2]]:
; CHECK-NEXT:    [[IV_2:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], %[[LOOP_2]] ]
; CHECK-NEXT:    [[IDX_A:%.*]] = shl nuw nsw i64 [[IV_2]], 1
; CHECK-NEXT:    [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IDX_A]]
; CHECK-NEXT:    [[L:%.*]] = load i32, ptr [[GEP_A]], align 4
; CHECK-NEXT:    [[GEP_B:%.*]] = getelementptr inbounds i32, ptr [[PTR_IV_LCSSA]], i64 [[IV_2]]
; CHECK-NEXT:    store i32 [[L]], ptr [[GEP_B]], align 4
; CHECK-NEXT:    [[IV_2_NEXT]] = add nuw nsw i64 [[IV_2]], 1
; CHECK-NEXT:    [[EC_2:%.*]] = icmp eq i64 [[IV_2_NEXT]], [[N]]
; CHECK-NEXT:    br i1 [[EC_2]], label %[[EXIT]], label %[[LOOP_2]], !llvm.loop [[LOOP8:![0-9]+]]
; CHECK:       [[EXIT]]:
; CHECK-NEXT:    ret void
;
entry:
  br label %loop.1

loop.1:
  %ptr.iv = phi ptr [ %b, %entry ], [ %ptr.iv.next, %loop.1 ]
  %iv.1 = phi i64 [ 0, %entry ], [ %iv.1.next, %loop.1 ]
  call void @use(i64 %iv.1)
  %ptr.iv.next = getelementptr inbounds i8, ptr %ptr.iv, i64 12
  %iv.1.next = add nuw i64 %iv.1, 1
  %ec.1 = icmp ugt i64 %iv.1, %m
  br i1 %ec.1, label %ph.2, label %loop.1

ph.2:
  br label %loop.2

loop.2:
  %iv.2 = phi i64 [ 0, %ph.2 ], [ %iv.2.next, %loop.2 ]
  %idx.a = shl nuw nsw i64 %iv.2, 1
  %gep.a = getelementptr inbounds i32, ptr %a, i64 %idx.a
  %l = load i32, ptr %gep.a, align 4
  %gep.b = getelementptr inbounds i32, ptr %ptr.iv, i64 %iv.2
  store i32 %l, ptr %gep.b, align 4
  %iv.2.next = add nuw nsw i64 %iv.2, 1
  %ec.2 = icmp eq i64 %iv.2.next, %n
  br i1 %ec.2, label %exit, label %loop.2

exit:
  ret void
}

define void @bound_is_trunc_of_sibling_loop_iv_multi_exit(ptr %a, ptr %b, i64 %n) {
; CHECK-LABEL: define void @bound_is_trunc_of_sibling_loop_iv_multi_exit(
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*]]:
; CHECK-NEXT:    br label %[[LOOP_1:.*]]
; CHECK:       [[LOOP_1]]:
; CHECK-NEXT:    [[IV_1:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP_1_LATCH:.*]] ]
; CHECK-NEXT:    [[EC_1:%.*]] = icmp uge i64 [[IV_1]], [[N]]
; CHECK-NEXT:    br i1 [[EC_1]], label %[[PH_2:.*]], label %[[LOOP_1_BODY:.*]]
; CHECK:       [[LOOP_1_BODY]]:
; CHECK-NEXT:    [[C:%.*]] = call i1 @cond(i64 [[IV_1]])
; CHECK-NEXT:    br i1 [[C]], label %[[PH_2]], label %[[LOOP_1_LATCH]]
; CHECK:       [[LOOP_1_LATCH]]:
; CHECK-NEXT:    [[IV_1_NEXT]] = add nuw i64 [[IV_1]], 1
; CHECK-NEXT:    br label %[[LOOP_1]]
; CHECK:       [[PH_2]]:
; CHECK-NEXT:    [[IV_1_LCSSA:%.*]] = phi i64 [ [[IV_1]], %[[LOOP_1_BODY]] ], [ [[IV_1]], %[[LOOP_1]] ]
; CHECK-NEXT:    br label %[[VECTOR_MEMCHECK:.*]]
; CHECK:       [[VECTOR_MEMCHECK]]:
; CHECK-NEXT:    [[SCEVGEP:%.*]] = getelementptr i8, ptr [[A]], i64 508
; CHECK-NEXT:    [[TMP0:%.*]] = shl i64 [[IV_1]], 1
; CHECK-NEXT:    [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
; CHECK-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
; CHECK-NEXT:    [[TMP3:%.*]] = shl nuw nsw i64 [[TMP2]], 2
; CHECK-NEXT:    [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP3]]
; CHECK-NEXT:    [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[B]], i64 256
; CHECK-NEXT:    [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[SCEVGEP2]], i64 [[TMP3]]
; CHECK-NEXT:    [[BOUND0:%.*]] = icmp ult ptr [[A]], [[SCEVGEP3]]
; CHECK-NEXT:    [[BOUND1:%.*]] = icmp ult ptr [[SCEVGEP1]], [[SCEVGEP]]
; CHECK-NEXT:    [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
; CHECK-NEXT:    br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK:       [[VECTOR_PH]]:
; CHECK-NEXT:    [[TMP4:%.*]] = trunc i64 [[IV_1_LCSSA]] to i32
; CHECK-NEXT:    [[TMP5:%.*]] = shl i32 [[TMP4]], 1
; CHECK-NEXT:    [[TMP6:%.*]] = zext i32 [[TMP5]] to i64
; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
; CHECK:       [[VECTOR_BODY]]:
; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT:    [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT:    [[TMP7:%.*]] = add i64 [[TMP6]], [[INDEX]]
; CHECK-NEXT:    [[TMP8:%.*]] = getelementptr i32, ptr [[B]], i64 [[TMP7]]
; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP8]], align 4, !alias.scope [[META9:![0-9]+]]
; CHECK-NEXT:    [[TMP9:%.*]] = shl nuw nsw <4 x i64> [[VEC_IND]], splat (i64 1)
; CHECK-NEXT:    [[TMP10:%.*]] = extractelement <4 x i64> [[TMP9]], i64 0
; CHECK-NEXT:    [[TMP11:%.*]] = getelementptr i32, ptr [[A]], i64 [[TMP10]]
; CHECK-NEXT:    [[TMP12:%.*]] = extractelement <4 x i64> [[TMP9]], i64 1
; CHECK-NEXT:    [[TMP13:%.*]] = getelementptr i32, ptr [[A]], i64 [[TMP12]]
; CHECK-NEXT:    [[TMP14:%.*]] = extractelement <4 x i64> [[TMP9]], i64 2
; CHECK-NEXT:    [[TMP15:%.*]] = getelementptr i32, ptr [[A]], i64 [[TMP14]]
; CHECK-NEXT:    [[TMP16:%.*]] = extractelement <4 x i64> [[TMP9]], i64 3
; CHECK-NEXT:    [[TMP17:%.*]] = getelementptr i32, ptr [[A]], i64 [[TMP16]]
; CHECK-NEXT:    [[TMP18:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i64 0
; CHECK-NEXT:    store i32 [[TMP18]], ptr [[TMP11]], align 4, !alias.scope [[META12:![0-9]+]], !noalias [[META9]]
; CHECK-NEXT:    [[TMP19:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i64 1
; CHECK-NEXT:    store i32 [[TMP19]], ptr [[TMP13]], align 4, !alias.scope [[META12]], !noalias [[META9]]
; CHECK-NEXT:    [[TMP20:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i64 2
; CHECK-NEXT:    store i32 [[TMP20]], ptr [[TMP15]], align 4, !alias.scope [[META12]], !noalias [[META9]]
; CHECK-NEXT:    [[TMP21:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i64 3
; CHECK-NEXT:    store i32 [[TMP21]], ptr [[TMP17]], align 4, !alias.scope [[META12]], !noalias [[META9]]
; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT:    [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4)
; CHECK-NEXT:    [[TMP22:%.*]] = icmp eq i64 [[INDEX_NEXT]], 64
; CHECK-NEXT:    br i1 [[TMP22]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
; CHECK:       [[MIDDLE_BLOCK]]:
; CHECK-NEXT:    br label %[[EXIT:.*]]
; CHECK:       [[SCALAR_PH]]:
; CHECK-NEXT:    br label %[[LOOP_2:.*]]
; CHECK:       [[LOOP_2]]:
; CHECK-NEXT:    [[IV_2:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], %[[LOOP_2]] ]
; CHECK-NEXT:    [[T:%.*]] = trunc i64 [[IV_1_LCSSA]] to i32
; CHECK-NEXT:    [[T_SHL:%.*]] = shl i32 [[T]], 1
; CHECK-NEXT:    [[OFF:%.*]] = zext i32 [[T_SHL]] to i64
; CHECK-NEXT:    [[IDX_B:%.*]] = add i64 [[OFF]], [[IV_2]]
; CHECK-NEXT:    [[GEP_B:%.*]] = getelementptr i32, ptr [[B]], i64 [[IDX_B]]
; CHECK-NEXT:    [[L:%.*]] = load i32, ptr [[GEP_B]], align 4
; CHECK-NEXT:    [[IDX_A:%.*]] = shl nuw nsw i64 [[IV_2]], 1
; CHECK-NEXT:    [[GEP_A:%.*]] = getelementptr i32, ptr [[A]], i64 [[IDX_A]]
; CHECK-NEXT:    store i32 [[L]], ptr [[GEP_A]], align 4
; CHECK-NEXT:    [[IV_2_NEXT]] = add nuw nsw i64 [[IV_2]], 1
; CHECK-NEXT:    [[EC_2:%.*]] = icmp eq i64 [[IV_2_NEXT]], 64
; CHECK-NEXT:    br i1 [[EC_2]], label %[[EXIT]], label %[[LOOP_2]], !llvm.loop [[LOOP15:![0-9]+]]
; CHECK:       [[EXIT]]:
; CHECK-NEXT:    ret void
;
entry:
  br label %loop.1

loop.1:
  %iv.1 = phi i64 [ 0, %entry ], [ %iv.1.next, %loop.1.latch ]
  %ec.1 = icmp uge i64 %iv.1, %n
  br i1 %ec.1, label %ph.2, label %loop.1.body

loop.1.body:
  %c = call i1 @cond(i64 %iv.1)
  br i1 %c, label %ph.2, label %loop.1.latch

loop.1.latch:
  %iv.1.next = add nuw i64 %iv.1, 1
  br label %loop.1

ph.2:
  br label %loop.2

loop.2:
  %iv.2 = phi i64 [ 0, %ph.2 ], [ %iv.2.next, %loop.2 ]
  %t = trunc i64 %iv.1 to i32
  %t.shl = shl i32 %t, 1
  %off = zext i32 %t.shl to i64
  %idx.b = add i64 %off, %iv.2
  %gep.b = getelementptr i32, ptr %b, i64 %idx.b
  %l = load i32, ptr %gep.b, align 4
  %idx.a = shl nuw nsw i64 %iv.2, 1
  %gep.a = getelementptr i32, ptr %a, i64 %idx.a
  store i32 %l, ptr %gep.a, align 4
  %iv.2.next = add nuw nsw i64 %iv.2, 1
  %ec.2 = icmp eq i64 %iv.2.next, 64
  br i1 %ec.2, label %exit, label %loop.2

exit:
  ret void
}

declare void @use(i64)
declare i1 @cond(i64)