test/Transforms/LoopVectorize/fmax-without-fast-math-flags-tail-folding.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -force-target-supports-masked-memory-ops -force-tail-folding-style=data-and-control -tail-folding-policy=prefer-fold-tail -S %s | FileCheck --check-prefix=IC1 %s
; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=2 -force-target-supports-masked-memory-ops -force-tail-folding-style=data-and-control -tail-folding-policy=prefer-fold-tail -S %s | FileCheck --check-prefix=IC2 %s

; Test fmaxnum reduction with the active-lane-mask controlling the loop exit.
; FIXME: Exit condition of loop is currently not set correctly.
define float @fmaxnum(ptr %src, i64 %n) {
; IC1-LABEL: define float @fmaxnum(
; IC1-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {
; IC1-NEXT:  [[ENTRY:.*:]]
; IC1-NEXT:    br label %[[VECTOR_PH:.*]]
; IC1:       [[VECTOR_PH]]:
; IC1-NEXT:    [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 0, i64 [[N]])
; IC1-NEXT:    [[TRIP_COUNT_MINUS_VF:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[N]], i64 4)
; IC1-NEXT:    br label %[[VECTOR_BODY:.*]]
; IC1:       [[VECTOR_BODY]]:
; IC1-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; IC1-NEXT:    [[ACTIVE_LANE_MASK:%.*]] = phi <4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], %[[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[VECTOR_BODY]] ]
; IC1-NEXT:    [[VEC_PHI:%.*]] = phi <4 x float> [ splat (float -1.000000e+07), %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ]
; IC1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw float, ptr [[SRC]], i64 [[INDEX]]
; IC1-NEXT:    [[WIDE_MASKED_LOAD:%.*]] = call <4 x float> @llvm.masked.load.v4f32.p0(ptr align 4 [[TMP0]], <4 x i1> [[ACTIVE_LANE_MASK]], <4 x float> poison)
; IC1-NEXT:    [[TMP1:%.*]] = freeze <4 x float> [[WIDE_MASKED_LOAD]]
; IC1-NEXT:    [[TMP2]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[TMP1]], <4 x float> [[VEC_PHI]])
; IC1-NEXT:    [[TMP3:%.*]] = fcmp uno <4 x float> [[TMP1]], [[TMP1]]
; IC1-NEXT:    [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP3]])
; IC1-NEXT:    [[ACTIVE_LANE_MASK_NEXT]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 [[INDEX]], i64 [[TRIP_COUNT_MINUS_VF]])
; IC1-NEXT:    [[TMP5:%.*]] = extractelement <4 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 0
; IC1-NEXT:    [[TMP6:%.*]] = xor i1 [[TMP5]], true
; IC1-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 4
; IC1-NEXT:    br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; IC1:       [[MIDDLE_BLOCK]]:
; IC1-NEXT:    [[TMP7:%.*]] = select <4 x i1> [[ACTIVE_LANE_MASK]], <4 x float> [[TMP2]], <4 x float> [[VEC_PHI]]
; IC1-NEXT:    [[TMP8:%.*]] = select i1 [[TMP4]], <4 x float> [[VEC_PHI]], <4 x float> [[TMP7]]
; IC1-NEXT:    [[TMP9:%.*]] = select i1 [[TMP4]], i64 [[INDEX]], i64 [[N]]
; IC1-NEXT:    [[TMP10:%.*]] = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> [[TMP8]])
; IC1-NEXT:    [[TMP11:%.*]] = xor i1 [[TMP4]], true
; IC1-NEXT:    br i1 [[TMP11]], label %[[EXIT:.*]], label %[[SCALAR_PH:.*]]
; IC1:       [[SCALAR_PH]]:
; IC1-NEXT:    br label %[[LOOP:.*]]
; IC1:       [[LOOP]]:
; IC1-NEXT:    [[IV:%.*]] = phi i64 [ [[TMP9]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; IC1-NEXT:    [[MAX:%.*]] = phi float [ [[TMP10]], %[[SCALAR_PH]] ], [ [[MAX_NEXT:%.*]], %[[LOOP]] ]
; IC1-NEXT:    [[GEP_SRC:%.*]] = getelementptr inbounds nuw float, ptr [[SRC]], i64 [[IV]]
; IC1-NEXT:    [[L:%.*]] = load float, ptr [[GEP_SRC]], align 4
; IC1-NEXT:    [[MAX_NEXT]] = call float @llvm.maxnum.f32(float [[L]], float [[MAX]])
; IC1-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; IC1-NEXT:    [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; IC1-NEXT:    br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
; IC1:       [[EXIT]]:
; IC1-NEXT:    [[MAX_NEXT_LCSSA:%.*]] = phi float [ [[MAX_NEXT]], %[[LOOP]] ], [ [[TMP10]], %[[MIDDLE_BLOCK]] ]
; IC1-NEXT:    ret float [[MAX_NEXT_LCSSA]]
;
; IC2-LABEL: define float @fmaxnum(
; IC2-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {
; IC2-NEXT:  [[ENTRY:.*:]]
; IC2-NEXT:    br label %[[VECTOR_PH:.*]]
; IC2:       [[VECTOR_PH]]:
; IC2-NEXT:    [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 0, i64 [[N]])
; IC2-NEXT:    [[EXTRACT_ENTRY_ALM_PART:%.*]] = call <4 x i1> @llvm.vector.extract.v4i1.v8i1(<8 x i1> [[ACTIVE_LANE_MASK_ENTRY]], i64 0)
; IC2-NEXT:    [[EXTRACT_ENTRY_ALM_PART1:%.*]] = call <4 x i1> @llvm.vector.extract.v4i1.v8i1(<8 x i1> [[ACTIVE_LANE_MASK_ENTRY]], i64 4)
; IC2-NEXT:    [[TRIP_COUNT_MINUS_VF:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[N]], i64 8)
; IC2-NEXT:    br label %[[VECTOR_BODY:.*]]
; IC2:       [[VECTOR_BODY]]:
; IC2-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; IC2-NEXT:    [[ACTIVE_LANE_MASK:%.*]] = phi <4 x i1> [ [[EXTRACT_ENTRY_ALM_PART]], %[[VECTOR_PH]] ], [ [[EXTRACT_NEXT_ALM_PART:%.*]], %[[VECTOR_BODY]] ]
; IC2-NEXT:    [[ACTIVE_LANE_MASK2:%.*]] = phi <4 x i1> [ [[EXTRACT_ENTRY_ALM_PART1]], %[[VECTOR_PH]] ], [ [[EXTRACT_NEXT_ALM_PART5:%.*]], %[[VECTOR_BODY]] ]
; IC2-NEXT:    [[VEC_PHI:%.*]] = phi <4 x float> [ splat (float -1.000000e+07), %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ]
; IC2-NEXT:    [[VEC_PHI3:%.*]] = phi <4 x float> [ splat (float -1.000000e+07), %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]
; IC2-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw float, ptr [[SRC]], i64 [[INDEX]]
; IC2-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP0]], i64 16
; IC2-NEXT:    [[WIDE_MASKED_LOAD:%.*]] = call <4 x float> @llvm.masked.load.v4f32.p0(ptr align 4 [[TMP0]], <4 x i1> [[ACTIVE_LANE_MASK]], <4 x float> poison)
; IC2-NEXT:    [[WIDE_MASKED_LOAD4:%.*]] = call <4 x float> @llvm.masked.load.v4f32.p0(ptr align 4 [[TMP1]], <4 x i1> [[ACTIVE_LANE_MASK2]], <4 x float> poison)
; IC2-NEXT:    [[TMP2:%.*]] = freeze <4 x float> [[WIDE_MASKED_LOAD]]
; IC2-NEXT:    [[TMP3:%.*]] = freeze <4 x float> [[WIDE_MASKED_LOAD4]]
; IC2-NEXT:    [[TMP4]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[TMP2]], <4 x float> [[VEC_PHI]])
; IC2-NEXT:    [[TMP5]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[TMP3]], <4 x float> [[VEC_PHI3]])
; IC2-NEXT:    [[TMP6:%.*]] = fcmp uno <4 x float> [[TMP2]], [[TMP3]]
; IC2-NEXT:    [[TMP7:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP6]])
; IC2-NEXT:    [[ACTIVE_LANE_MASK_NEXT:%.*]] = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 [[INDEX]], i64 [[TRIP_COUNT_MINUS_VF]])
; IC2-NEXT:    [[EXTRACT_NEXT_ALM_PART]] = call <4 x i1> @llvm.vector.extract.v4i1.v8i1(<8 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 0)
; IC2-NEXT:    [[EXTRACT_NEXT_ALM_PART5]] = call <4 x i1> @llvm.vector.extract.v4i1.v8i1(<8 x i1> [[ACTIVE_LANE_MASK_NEXT]], i64 4)
; IC2-NEXT:    [[TMP8:%.*]] = extractelement <4 x i1> [[EXTRACT_NEXT_ALM_PART]], i64 0
; IC2-NEXT:    [[TMP9:%.*]] = xor i1 [[TMP8]], true
; IC2-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 8
; IC2-NEXT:    br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; IC2:       [[MIDDLE_BLOCK]]:
; IC2-NEXT:    [[TMP10:%.*]] = select <4 x i1> [[ACTIVE_LANE_MASK]], <4 x float> [[TMP4]], <4 x float> [[VEC_PHI]]
; IC2-NEXT:    [[TMP11:%.*]] = select <4 x i1> [[ACTIVE_LANE_MASK2]], <4 x float> [[TMP5]], <4 x float> [[VEC_PHI3]]
; IC2-NEXT:    [[TMP12:%.*]] = select i1 [[TMP7]], <4 x float> [[VEC_PHI]], <4 x float> [[TMP10]]
; IC2-NEXT:    [[TMP13:%.*]] = select i1 [[TMP7]], <4 x float> [[VEC_PHI3]], <4 x float> [[TMP11]]
; IC2-NEXT:    [[TMP14:%.*]] = select i1 [[TMP7]], i64 [[INDEX]], i64 [[N]]
; IC2-NEXT:    [[RDX_MINMAX:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[TMP12]], <4 x float> [[TMP13]])
; IC2-NEXT:    [[TMP15:%.*]] = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> [[RDX_MINMAX]])
; IC2-NEXT:    [[TMP16:%.*]] = xor i1 [[TMP7]], true
; IC2-NEXT:    br i1 [[TMP16]], label %[[EXIT:.*]], label %[[SCALAR_PH:.*]]
; IC2:       [[SCALAR_PH]]:
; IC2-NEXT:    br label %[[LOOP:.*]]
; IC2:       [[LOOP]]:
; IC2-NEXT:    [[IV:%.*]] = phi i64 [ [[TMP14]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; IC2-NEXT:    [[MAX:%.*]] = phi float [ [[TMP15]], %[[SCALAR_PH]] ], [ [[MAX_NEXT:%.*]], %[[LOOP]] ]
; IC2-NEXT:    [[GEP_SRC:%.*]] = getelementptr inbounds nuw float, ptr [[SRC]], i64 [[IV]]
; IC2-NEXT:    [[L:%.*]] = load float, ptr [[GEP_SRC]], align 4
; IC2-NEXT:    [[MAX_NEXT]] = call float @llvm.maxnum.f32(float [[L]], float [[MAX]])
; IC2-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; IC2-NEXT:    [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; IC2-NEXT:    br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
; IC2:       [[EXIT]]:
; IC2-NEXT:    [[MAX_NEXT_LCSSA:%.*]] = phi float [ [[MAX_NEXT]], %[[LOOP]] ], [ [[TMP15]], %[[MIDDLE_BLOCK]] ]
; IC2-NEXT:    ret float [[MAX_NEXT_LCSSA]]
;
entry:
  br label %loop

loop:
  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
  %max = phi float [ -1.000000e+07, %entry ], [ %max.next, %loop ]
  %gep.src = getelementptr inbounds nuw float, ptr %src, i64 %iv
  %l = load float, ptr %gep.src, align 4
  %max.next = call float @llvm.maxnum.f32(float %l, float %max)
  %iv.next = add nuw nsw i64 %iv, 1
  %ec = icmp eq i64 %iv.next, %n
  br i1 %ec, label %exit, label %loop

exit:
  ret float %max.next
}