test/Transforms/LoopVectorize/alloca-in-loop.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "^scalar.ph" --version 6
; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=2 -S %s | FileCheck --check-prefix=VF4IC2 %s
; RUN: opt -passes=loop-vectorize -force-vector-width=1 -force-vector-interleave=2 -S %s | FileCheck --check-prefix=VF1IC2 %s

; Each execution of an alloca creates a distinct allocation, so each lane and
; part must execute its own alloca.

; FIXME: currently miscompiled.
define void @alloca_address_stored(ptr noalias %dst, i64 %n) {
; VF4IC2-LABEL: define void @alloca_address_stored(
; VF4IC2-SAME: ptr noalias [[DST:%.*]], i64 [[N:%.*]]) {
; VF4IC2-NEXT:  [[ENTRY:.*:]]
; VF4IC2-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8
; VF4IC2-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; VF4IC2:       [[VECTOR_PH]]:
; VF4IC2-NEXT:    [[TMP0:%.*]] = and i64 [[N]], 7
; VF4IC2-NEXT:    [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]]
; VF4IC2-NEXT:    br label %[[VECTOR_BODY:.*]]
; VF4IC2:       [[VECTOR_BODY]]:
; VF4IC2-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; VF4IC2-NEXT:    [[TMP1:%.*]] = trunc i64 [[INDEX]] to i32
; VF4IC2-NEXT:    [[TMP2:%.*]] = add i32 [[TMP1]], 1
; VF4IC2-NEXT:    [[TMP3:%.*]] = add i32 [[TMP1]], 2
; VF4IC2-NEXT:    [[TMP4:%.*]] = add i32 [[TMP1]], 3
; VF4IC2-NEXT:    [[TMP5:%.*]] = add i32 [[TMP1]], 4
; VF4IC2-NEXT:    [[TMP6:%.*]] = add i32 [[TMP1]], 5
; VF4IC2-NEXT:    [[TMP7:%.*]] = add i32 [[TMP1]], 6
; VF4IC2-NEXT:    [[TMP8:%.*]] = add i32 [[TMP1]], 7
; VF4IC2-NEXT:    [[TMP9:%.*]] = alloca [8 x i8], align 16
; VF4IC2-NEXT:    [[TMP13:%.*]] = alloca [8 x i8], align 16
; VF4IC2-NEXT:    [[TMP16:%.*]] = alloca [8 x i8], align 16
; VF4IC2-NEXT:    [[TMP25:%.*]] = alloca [8 x i8], align 16
; VF4IC2-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x ptr> poison, ptr [[TMP9]], i64 0
; VF4IC2-NEXT:    [[TMP14:%.*]] = insertelement <4 x ptr> [[BROADCAST_SPLATINSERT]], ptr [[TMP13]], i64 1
; VF4IC2-NEXT:    [[TMP15:%.*]] = insertelement <4 x ptr> [[TMP14]], ptr [[TMP16]], i64 2
; VF4IC2-NEXT:    [[BROADCAST_SPLAT:%.*]] = insertelement <4 x ptr> [[TMP15]], ptr [[TMP25]], i64 3
; VF4IC2-NEXT:    [[TMP17:%.*]] = alloca [8 x i8], align 16
; VF4IC2-NEXT:    [[TMP18:%.*]] = alloca [8 x i8], align 16
; VF4IC2-NEXT:    [[TMP19:%.*]] = alloca [8 x i8], align 16
; VF4IC2-NEXT:    [[TMP20:%.*]] = alloca [8 x i8], align 16
; VF4IC2-NEXT:    [[TMP21:%.*]] = insertelement <4 x ptr> poison, ptr [[TMP17]], i64 0
; VF4IC2-NEXT:    [[TMP22:%.*]] = insertelement <4 x ptr> [[TMP21]], ptr [[TMP18]], i64 1
; VF4IC2-NEXT:    [[TMP23:%.*]] = insertelement <4 x ptr> [[TMP22]], ptr [[TMP19]], i64 2
; VF4IC2-NEXT:    [[TMP24:%.*]] = insertelement <4 x ptr> [[TMP23]], ptr [[TMP20]], i64 3
; VF4IC2-NEXT:    [[TMP10:%.*]] = getelementptr inbounds ptr, ptr [[DST]], i64 [[INDEX]]
; VF4IC2-NEXT:    [[TMP11:%.*]] = getelementptr inbounds ptr, ptr [[TMP10]], i64 4
; VF4IC2-NEXT:    store <4 x ptr> [[BROADCAST_SPLAT]], ptr [[TMP10]], align 8
; VF4IC2-NEXT:    store <4 x ptr> [[TMP24]], ptr [[TMP11]], align 8
; VF4IC2-NEXT:    store i32 [[TMP1]], ptr [[TMP9]], align 4
; VF4IC2-NEXT:    store i32 [[TMP2]], ptr [[TMP13]], align 4
; VF4IC2-NEXT:    store i32 [[TMP3]], ptr [[TMP16]], align 4
; VF4IC2-NEXT:    store i32 [[TMP4]], ptr [[TMP25]], align 4
; VF4IC2-NEXT:    store i32 [[TMP5]], ptr [[TMP17]], align 4
; VF4IC2-NEXT:    store i32 [[TMP6]], ptr [[TMP18]], align 4
; VF4IC2-NEXT:    store i32 [[TMP7]], ptr [[TMP19]], align 4
; VF4IC2-NEXT:    store i32 [[TMP8]], ptr [[TMP20]], align 4
; VF4IC2-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
; VF4IC2-NEXT:    [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; VF4IC2-NEXT:    br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; VF4IC2:       [[MIDDLE_BLOCK]]:
; VF4IC2-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; VF4IC2-NEXT:    br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]]
; VF4IC2:       [[SCALAR_PH]]:
;
; VF1IC2-LABEL: define void @alloca_address_stored(
; VF1IC2-SAME: ptr noalias [[DST:%.*]], i64 [[N:%.*]]) {
; VF1IC2-NEXT:  [[ENTRY:.*:]]
; VF1IC2-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2
; VF1IC2-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; VF1IC2:       [[VECTOR_PH]]:
; VF1IC2-NEXT:    [[TMP0:%.*]] = and i64 [[N]], 1
; VF1IC2-NEXT:    [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]]
; VF1IC2-NEXT:    br label %[[VECTOR_BODY:.*]]
; VF1IC2:       [[VECTOR_BODY]]:
; VF1IC2-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; VF1IC2-NEXT:    [[TMP1:%.*]] = add i64 [[INDEX]], 1
; VF1IC2-NEXT:    [[TMP2:%.*]] = trunc i64 [[INDEX]] to i32
; VF1IC2-NEXT:    [[TMP3:%.*]] = add i32 [[TMP2]], 1
; VF1IC2-NEXT:    [[TMP4:%.*]] = alloca [8 x i8], align 16
; VF1IC2-NEXT:    [[TMP8:%.*]] = alloca [8 x i8], align 16
; VF1IC2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[DST]], i64 [[INDEX]]
; VF1IC2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[DST]], i64 [[TMP1]]
; VF1IC2-NEXT:    store ptr [[TMP4]], ptr [[TMP5]], align 8
; VF1IC2-NEXT:    store ptr [[TMP8]], ptr [[TMP6]], align 8
; VF1IC2-NEXT:    store i32 [[TMP2]], ptr [[TMP4]], align 4
; VF1IC2-NEXT:    store i32 [[TMP3]], ptr [[TMP8]], align 4
; VF1IC2-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
; VF1IC2-NEXT:    [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; VF1IC2-NEXT:    br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; VF1IC2:       [[MIDDLE_BLOCK]]:
; VF1IC2-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; VF1IC2-NEXT:    br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]]
; VF1IC2:       [[SCALAR_PH]]:
;
entry:
  br label %loop

loop:
  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
  %a = alloca [8 x i8], align 16
  %gep = getelementptr inbounds ptr, ptr %dst, i64 %iv
  store ptr %a, ptr %gep, align 8
  %t = trunc i64 %iv to i32
  store i32 %t, ptr %a, align 4
  %iv.next = add nuw nsw i64 %iv, 1
  %ec = icmp eq i64 %iv.next, %n
  br i1 %ec, label %exit, label %loop

exit:
  ret void
}

; Allocas with different allocated types must not be merged.
; FIXME: currently miscompiled.
define void @two_allocas_different_types(ptr noalias %dst.a, ptr noalias %dst.b, i64 %n) {
; VF4IC2-LABEL: define void @two_allocas_different_types(
; VF4IC2-SAME: ptr noalias [[DST_A:%.*]], ptr noalias [[DST_B:%.*]], i64 [[N:%.*]]) {
; VF4IC2-NEXT:  [[ENTRY:.*:]]
; VF4IC2-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8
; VF4IC2-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; VF4IC2:       [[VECTOR_PH]]:
; VF4IC2-NEXT:    [[TMP0:%.*]] = and i64 [[N]], 7
; VF4IC2-NEXT:    [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]]
; VF4IC2-NEXT:    br label %[[VECTOR_BODY:.*]]
; VF4IC2:       [[VECTOR_BODY]]:
; VF4IC2-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; VF4IC2-NEXT:    [[TMP1:%.*]] = alloca i32, align 4
; VF4IC2-NEXT:    [[TMP8:%.*]] = alloca i32, align 4
; VF4IC2-NEXT:    [[TMP33:%.*]] = alloca i32, align 4
; VF4IC2-NEXT:    [[TMP34:%.*]] = alloca i32, align 4
; VF4IC2-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x ptr> poison, ptr [[TMP1]], i64 0
; VF4IC2-NEXT:    [[TMP35:%.*]] = insertelement <4 x ptr> [[BROADCAST_SPLATINSERT]], ptr [[TMP8]], i64 1
; VF4IC2-NEXT:    [[TMP7:%.*]] = insertelement <4 x ptr> [[TMP35]], ptr [[TMP33]], i64 2
; VF4IC2-NEXT:    [[BROADCAST_SPLAT:%.*]] = insertelement <4 x ptr> [[TMP7]], ptr [[TMP34]], i64 3
; VF4IC2-NEXT:    [[TMP9:%.*]] = alloca i32, align 4
; VF4IC2-NEXT:    [[TMP10:%.*]] = alloca i32, align 4
; VF4IC2-NEXT:    [[TMP11:%.*]] = alloca i32, align 4
; VF4IC2-NEXT:    [[TMP12:%.*]] = alloca i32, align 4
; VF4IC2-NEXT:    [[TMP13:%.*]] = insertelement <4 x ptr> poison, ptr [[TMP9]], i64 0
; VF4IC2-NEXT:    [[TMP14:%.*]] = insertelement <4 x ptr> [[TMP13]], ptr [[TMP10]], i64 1
; VF4IC2-NEXT:    [[TMP15:%.*]] = insertelement <4 x ptr> [[TMP14]], ptr [[TMP11]], i64 2
; VF4IC2-NEXT:    [[TMP16:%.*]] = insertelement <4 x ptr> [[TMP15]], ptr [[TMP12]], i64 3
; VF4IC2-NEXT:    [[TMP17:%.*]] = alloca i64, align 4
; VF4IC2-NEXT:    [[TMP18:%.*]] = alloca i64, align 4
; VF4IC2-NEXT:    [[TMP19:%.*]] = alloca i64, align 4
; VF4IC2-NEXT:    [[TMP20:%.*]] = alloca i64, align 4
; VF4IC2-NEXT:    [[TMP21:%.*]] = insertelement <4 x ptr> poison, ptr [[TMP17]], i64 0
; VF4IC2-NEXT:    [[TMP22:%.*]] = insertelement <4 x ptr> [[TMP21]], ptr [[TMP18]], i64 1
; VF4IC2-NEXT:    [[TMP23:%.*]] = insertelement <4 x ptr> [[TMP22]], ptr [[TMP19]], i64 2
; VF4IC2-NEXT:    [[TMP24:%.*]] = insertelement <4 x ptr> [[TMP23]], ptr [[TMP20]], i64 3
; VF4IC2-NEXT:    [[TMP25:%.*]] = alloca i64, align 4
; VF4IC2-NEXT:    [[TMP26:%.*]] = alloca i64, align 4
; VF4IC2-NEXT:    [[TMP27:%.*]] = alloca i64, align 4
; VF4IC2-NEXT:    [[TMP28:%.*]] = alloca i64, align 4
; VF4IC2-NEXT:    [[TMP29:%.*]] = insertelement <4 x ptr> poison, ptr [[TMP25]], i64 0
; VF4IC2-NEXT:    [[TMP30:%.*]] = insertelement <4 x ptr> [[TMP29]], ptr [[TMP26]], i64 1
; VF4IC2-NEXT:    [[TMP31:%.*]] = insertelement <4 x ptr> [[TMP30]], ptr [[TMP27]], i64 2
; VF4IC2-NEXT:    [[TMP32:%.*]] = insertelement <4 x ptr> [[TMP31]], ptr [[TMP28]], i64 3
; VF4IC2-NEXT:    [[TMP2:%.*]] = getelementptr inbounds ptr, ptr [[DST_A]], i64 [[INDEX]]
; VF4IC2-NEXT:    [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[TMP2]], i64 4
; VF4IC2-NEXT:    store <4 x ptr> [[BROADCAST_SPLAT]], ptr [[TMP2]], align 8
; VF4IC2-NEXT:    store <4 x ptr> [[TMP16]], ptr [[TMP3]], align 8
; VF4IC2-NEXT:    [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[DST_B]], i64 [[INDEX]]
; VF4IC2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[TMP4]], i64 4
; VF4IC2-NEXT:    store <4 x ptr> [[TMP24]], ptr [[TMP4]], align 8
; VF4IC2-NEXT:    store <4 x ptr> [[TMP32]], ptr [[TMP5]], align 8
; VF4IC2-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
; VF4IC2-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; VF4IC2-NEXT:    br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
; VF4IC2:       [[MIDDLE_BLOCK]]:
; VF4IC2-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; VF4IC2-NEXT:    br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]]
; VF4IC2:       [[SCALAR_PH]]:
;
; VF1IC2-LABEL: define void @two_allocas_different_types(
; VF1IC2-SAME: ptr noalias [[DST_A:%.*]], ptr noalias [[DST_B:%.*]], i64 [[N:%.*]]) {
; VF1IC2-NEXT:  [[ENTRY:.*:]]
; VF1IC2-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 2
; VF1IC2-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; VF1IC2:       [[VECTOR_PH]]:
; VF1IC2-NEXT:    [[TMP0:%.*]] = and i64 [[N]], 1
; VF1IC2-NEXT:    [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]]
; VF1IC2-NEXT:    br label %[[VECTOR_BODY:.*]]
; VF1IC2:       [[VECTOR_BODY]]:
; VF1IC2-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; VF1IC2-NEXT:    [[TMP1:%.*]] = add i64 [[INDEX]], 1
; VF1IC2-NEXT:    [[TMP2:%.*]] = alloca i32, align 4
; VF1IC2-NEXT:    [[TMP8:%.*]] = alloca i32, align 4
; VF1IC2-NEXT:    [[TMP9:%.*]] = alloca i64, align 4
; VF1IC2-NEXT:    [[TMP10:%.*]] = alloca i64, align 4
; VF1IC2-NEXT:    [[TMP3:%.*]] = getelementptr inbounds ptr, ptr [[DST_A]], i64 [[INDEX]]
; VF1IC2-NEXT:    [[TMP4:%.*]] = getelementptr inbounds ptr, ptr [[DST_A]], i64 [[TMP1]]
; VF1IC2-NEXT:    store ptr [[TMP2]], ptr [[TMP3]], align 8
; VF1IC2-NEXT:    store ptr [[TMP8]], ptr [[TMP4]], align 8
; VF1IC2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds ptr, ptr [[DST_B]], i64 [[INDEX]]
; VF1IC2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds ptr, ptr [[DST_B]], i64 [[TMP1]]
; VF1IC2-NEXT:    store ptr [[TMP9]], ptr [[TMP5]], align 8
; VF1IC2-NEXT:    store ptr [[TMP10]], ptr [[TMP6]], align 8
; VF1IC2-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
; VF1IC2-NEXT:    [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; VF1IC2-NEXT:    br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
; VF1IC2:       [[MIDDLE_BLOCK]]:
; VF1IC2-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; VF1IC2-NEXT:    br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]]
; VF1IC2:       [[SCALAR_PH]]:
;
entry:
  br label %loop

loop:
  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
  %a = alloca i32, align 4
  %b = alloca i64, align 4
  %gep.a = getelementptr inbounds ptr, ptr %dst.a, i64 %iv
  store ptr %a, ptr %gep.a, align 8
  %gep.b = getelementptr inbounds ptr, ptr %dst.b, i64 %iv
  store ptr %b, ptr %gep.b, align 8
  %iv.next = add nuw nsw i64 %iv, 1
  %ec = icmp eq i64 %iv.next, %n
  br i1 %ec, label %exit, label %loop

exit:
  ret void
}