test/Transforms/LoopVectorize/X86/compress-idioms.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "^scalar.ph:" --version 6
; RUN: opt < %s -mtriple=x86_64-- -mcpu=x86-64-v4 -passes=loop-vectorize -S | FileCheck %s --check-prefix=CHECK-V4
; RUN: opt < %s -mtriple=x86_64-- -mcpu=icelake-server -passes=loop-vectorize -S | FileCheck %s --check-prefix=CHECK-ICELAKE
; RUN: opt < %s -mtriple=x86_64-- -mcpu=znver4 -passes=loop-vectorize -S | FileCheck %s --check-prefix=CHECK-ZNVER4

define void @compress_store(ptr writeonly noalias %dst, ptr readonly %src, i32 %c, i64 %n) {
; CHECK-V4-LABEL: define void @compress_store(
; CHECK-V4-SAME: ptr noalias writeonly [[DST:%.*]], ptr readonly [[SRC:%.*]], i32 [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-V4-NEXT:  [[ENTRY:.*]]:
; CHECK-V4-NEXT:    br label %[[FOR_BODY:.*]]
; CHECK-V4:       [[FOR_BODY]]:
; CHECK-V4-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_INC:.*]] ]
; CHECK-V4-NEXT:    [[IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IDX_1:%.*]], %[[FOR_INC]] ]
; CHECK-V4-NEXT:    [[SRC_PTR:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[IV]]
; CHECK-V4-NEXT:    [[LOAD_SRC:%.*]] = load i32, ptr [[SRC_PTR]], align 4
; CHECK-V4-NEXT:    [[CMP:%.*]] = icmp slt i32 [[LOAD_SRC]], [[C]]
; CHECK-V4-NEXT:    br i1 [[CMP]], label %[[IF_THEN:.*]], label %[[FOR_INC]]
; CHECK-V4:       [[IF_THEN]]:
; CHECK-V4-NEXT:    [[DST_PTR:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IDX]]
; CHECK-V4-NEXT:    store i32 [[LOAD_SRC]], ptr [[DST_PTR]], align 4
; CHECK-V4-NEXT:    [[IDX_NEXT:%.*]] = add nsw i64 [[IDX]], 1
; CHECK-V4-NEXT:    br label %[[FOR_INC]]
; CHECK-V4:       [[FOR_INC]]:
; CHECK-V4-NEXT:    [[IDX_1]] = phi i64 [ [[IDX_NEXT]], %[[IF_THEN]] ], [ [[IDX]], %[[FOR_BODY]] ]
; CHECK-V4-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-V4-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; CHECK-V4-NEXT:    br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]]
; CHECK-V4:       [[EXIT]]:
; CHECK-V4-NEXT:    ret void
;
; CHECK-ICELAKE-LABEL: define void @compress_store(
; CHECK-ICELAKE-SAME: ptr noalias writeonly [[DST:%.*]], ptr readonly [[SRC:%.*]], i32 [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-ICELAKE-NEXT:  [[ENTRY:.*]]:
; CHECK-ICELAKE-NEXT:    br label %[[FOR_BODY:.*]]
; CHECK-ICELAKE:       [[FOR_BODY]]:
; CHECK-ICELAKE-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_INC:.*]] ]
; CHECK-ICELAKE-NEXT:    [[IDX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IDX_1:%.*]], %[[FOR_INC]] ]
; CHECK-ICELAKE-NEXT:    [[SRC_PTR:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[IV]]
; CHECK-ICELAKE-NEXT:    [[LOAD_SRC:%.*]] = load i32, ptr [[SRC_PTR]], align 4
; CHECK-ICELAKE-NEXT:    [[CMP:%.*]] = icmp slt i32 [[LOAD_SRC]], [[C]]
; CHECK-ICELAKE-NEXT:    br i1 [[CMP]], label %[[IF_THEN:.*]], label %[[FOR_INC]]
; CHECK-ICELAKE:       [[IF_THEN]]:
; CHECK-ICELAKE-NEXT:    [[DST_PTR:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IDX]]
; CHECK-ICELAKE-NEXT:    store i32 [[LOAD_SRC]], ptr [[DST_PTR]], align 4
; CHECK-ICELAKE-NEXT:    [[IDX_NEXT:%.*]] = add nsw i64 [[IDX]], 1
; CHECK-ICELAKE-NEXT:    br label %[[FOR_INC]]
; CHECK-ICELAKE:       [[FOR_INC]]:
; CHECK-ICELAKE-NEXT:    [[IDX_1]] = phi i64 [ [[IDX_NEXT]], %[[IF_THEN]] ], [ [[IDX]], %[[FOR_BODY]] ]
; CHECK-ICELAKE-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-ICELAKE-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; CHECK-ICELAKE-NEXT:    br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]]
; CHECK-ICELAKE:       [[EXIT]]:
; CHECK-ICELAKE-NEXT:    ret void
;
; CHECK-ZNVER4-LABEL: define void @compress_store(
; CHECK-ZNVER4-SAME: ptr noalias writeonly [[DST:%.*]], ptr readonly [[SRC:%.*]], i32 [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-ZNVER4-NEXT:  [[VECTOR_PH:.*]]:
; CHECK-ZNVER4-NEXT:    br label %[[VECTOR_BODY:.*]]
; CHECK-ZNVER4:       [[VECTOR_BODY]]:
; CHECK-ZNVER4-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[IV_NEXT:%.*]], %[[MIDDLE_BLOCK:.*]] ]
; CHECK-ZNVER4-NEXT:    [[CONDITIONAL_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[IDX_1:%.*]], %[[MIDDLE_BLOCK]] ]
; CHECK-ZNVER4-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]]
; CHECK-ZNVER4-NEXT:    [[LOAD_SRC:%.*]] = load i32, ptr [[TMP1]], align 4
; CHECK-ZNVER4-NEXT:    [[CMP:%.*]] = icmp slt i32 [[LOAD_SRC]], [[C]]
; CHECK-ZNVER4-NEXT:    br i1 [[CMP]], label %[[IF_THEN:.*]], label %[[MIDDLE_BLOCK]]
; CHECK-ZNVER4:       [[IF_THEN]]:
; CHECK-ZNVER4-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[CONDITIONAL_IV]]
; CHECK-ZNVER4-NEXT:    store i32 [[LOAD_SRC]], ptr [[TMP3]], align 4
; CHECK-ZNVER4-NEXT:    [[IDX_NEXT:%.*]] = add nsw i64 [[CONDITIONAL_IV]], 1
; CHECK-ZNVER4-NEXT:    br label %[[MIDDLE_BLOCK]]
; CHECK-ZNVER4:       [[MIDDLE_BLOCK]]:
; CHECK-ZNVER4-NEXT:    [[IDX_1]] = phi i64 [ [[IDX_NEXT]], %[[IF_THEN]] ], [ [[CONDITIONAL_IV]], %[[VECTOR_BODY]] ]
; CHECK-ZNVER4-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[INDEX]], 1
; CHECK-ZNVER4-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; CHECK-ZNVER4-NEXT:    br i1 [[EXITCOND_NOT]], label %[[SCALAR_PH:.*]], label %[[VECTOR_BODY]]
; CHECK-ZNVER4:       [[SCALAR_PH]]:
; CHECK-ZNVER4-NEXT:    ret void
;
entry:
  br label %for.body

for.body:
  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.inc ]
  %idx = phi i64 [ 0, %entry ], [ %idx.1, %for.inc ]
  %src.ptr = getelementptr inbounds i32, ptr %src, i64 %iv
  %load.src = load i32, ptr %src.ptr, align 4
  %cmp = icmp slt i32 %load.src, %c
  br i1 %cmp, label %if.then, label %for.inc

if.then:
  %dst.ptr = getelementptr inbounds i32, ptr %dst, i64 %idx
  store i32 %load.src, ptr %dst.ptr, align 4
  %idx.next = add nsw i64 %idx, 1
  br label %for.inc

for.inc:
  %idx.1 = phi i64 [ %idx.next, %if.then ], [ %idx, %for.body ]
  %iv.next = add nuw nsw i64 %iv, 1
  %exitcond.not = icmp eq i64 %iv.next, %n
  br i1 %exitcond.not, label %exit, label %for.body

exit:
  ret void
}

define void @expand_load(ptr noalias %dst, ptr readonly %src, i32 %c, i64 %n) {
; CHECK-V4-LABEL: define void @expand_load(
; CHECK-V4-SAME: ptr noalias [[DST:%.*]], ptr readonly [[SRC:%.*]], i32 [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
; CHECK-V4-NEXT:  [[VECTOR_PH:.*]]:
; CHECK-V4-NEXT:    br label %[[VECTOR_BODY:.*]]
; CHECK-V4:       [[VECTOR_BODY]]:
; CHECK-V4-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[IV_NEXT:%.*]], %[[MIDDLE_BLOCK:.*]] ]
; CHECK-V4-NEXT:    [[CONDITIONAL_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[IDX_1:%.*]], %[[MIDDLE_BLOCK]] ]
; CHECK-V4-NEXT:    [[DST_PTR:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IV]]
; CHECK-V4-NEXT:    [[LOAD_DST:%.*]] = load i32, ptr [[DST_PTR]], align 4
; CHECK-V4-NEXT:    [[CMP:%.*]] = icmp slt i32 [[LOAD_DST]], [[C]]
; CHECK-V4-NEXT:    br i1 [[CMP]], label %[[IF_THEN:.*]], label %[[MIDDLE_BLOCK]]
; CHECK-V4:       [[IF_THEN]]:
; CHECK-V4-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[CONDITIONAL_IV]]
; CHECK-V4-NEXT:    [[LOAD_SRC:%.*]] = load i32, ptr [[TMP3]], align 4
; CHECK-V4-NEXT:    store i32 [[LOAD_SRC]], ptr [[DST_PTR]], align 4
; CHECK-V4-NEXT:    [[IDX_NEXT:%.*]] = add nsw i64 [[CONDITIONAL_IV]], 1
; CHECK-V4-NEXT:    br label %[[MIDDLE_BLOCK]]
; CHECK-V4:       [[MIDDLE_BLOCK]]:
; CHECK-V4-NEXT:    [[IDX_1]] = phi i64 [ [[IDX_NEXT]], %[[IF_THEN]] ], [ [[CONDITIONAL_IV]], %[[VECTOR_BODY]] ]
; CHECK-V4-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-V4-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; CHECK-V4-NEXT:    br i1 [[EXITCOND_NOT]], label %[[SCALAR_PH:.*]], label %[[VECTOR_BODY]]
; CHECK-V4:       [[SCALAR_PH]]:
; CHECK-V4-NEXT:    ret void
;
; CHECK-ICELAKE-LABEL: define void @expand_load(
; CHECK-ICELAKE-SAME: ptr noalias [[DST:%.*]], ptr readonly [[SRC:%.*]], i32 [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
; CHECK-ICELAKE-NEXT:  [[VECTOR_PH:.*]]:
; CHECK-ICELAKE-NEXT:    br label %[[VECTOR_BODY:.*]]
; CHECK-ICELAKE:       [[VECTOR_BODY]]:
; CHECK-ICELAKE-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[IV_NEXT:%.*]], %[[MIDDLE_BLOCK:.*]] ]
; CHECK-ICELAKE-NEXT:    [[CONDITIONAL_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[IDX_1:%.*]], %[[MIDDLE_BLOCK]] ]
; CHECK-ICELAKE-NEXT:    [[DST_PTR:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IV]]
; CHECK-ICELAKE-NEXT:    [[LOAD_DST:%.*]] = load i32, ptr [[DST_PTR]], align 4
; CHECK-ICELAKE-NEXT:    [[CMP:%.*]] = icmp slt i32 [[LOAD_DST]], [[C]]
; CHECK-ICELAKE-NEXT:    br i1 [[CMP]], label %[[IF_THEN:.*]], label %[[MIDDLE_BLOCK]]
; CHECK-ICELAKE:       [[IF_THEN]]:
; CHECK-ICELAKE-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[CONDITIONAL_IV]]
; CHECK-ICELAKE-NEXT:    [[LOAD_SRC:%.*]] = load i32, ptr [[TMP3]], align 4
; CHECK-ICELAKE-NEXT:    store i32 [[LOAD_SRC]], ptr [[DST_PTR]], align 4
; CHECK-ICELAKE-NEXT:    [[IDX_NEXT:%.*]] = add nsw i64 [[CONDITIONAL_IV]], 1
; CHECK-ICELAKE-NEXT:    br label %[[MIDDLE_BLOCK]]
; CHECK-ICELAKE:       [[MIDDLE_BLOCK]]:
; CHECK-ICELAKE-NEXT:    [[IDX_1]] = phi i64 [ [[IDX_NEXT]], %[[IF_THEN]] ], [ [[CONDITIONAL_IV]], %[[VECTOR_BODY]] ]
; CHECK-ICELAKE-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-ICELAKE-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; CHECK-ICELAKE-NEXT:    br i1 [[EXITCOND_NOT]], label %[[SCALAR_PH:.*]], label %[[VECTOR_BODY]]
; CHECK-ICELAKE:       [[SCALAR_PH]]:
; CHECK-ICELAKE-NEXT:    ret void
;
; CHECK-ZNVER4-LABEL: define void @expand_load(
; CHECK-ZNVER4-SAME: ptr noalias [[DST:%.*]], ptr readonly [[SRC:%.*]], i32 [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
; CHECK-ZNVER4-NEXT:  [[VEC_EPILOG_SCALAR_PH:.*]]:
; CHECK-ZNVER4-NEXT:    br label %[[FOR_BODY:.*]]
; CHECK-ZNVER4:       [[FOR_BODY]]:
; CHECK-ZNVER4-NEXT:    [[IV:%.*]] = phi i64 [ 0, %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_INC:.*]] ]
; CHECK-ZNVER4-NEXT:    [[IDX:%.*]] = phi i64 [ 0, %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IDX_1:%.*]], %[[FOR_INC]] ]
; CHECK-ZNVER4-NEXT:    [[DST_PTR:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IV]]
; CHECK-ZNVER4-NEXT:    [[LOAD_DST:%.*]] = load i32, ptr [[DST_PTR]], align 4
; CHECK-ZNVER4-NEXT:    [[CMP:%.*]] = icmp slt i32 [[LOAD_DST]], [[C]]
; CHECK-ZNVER4-NEXT:    br i1 [[CMP]], label %[[IF_THEN:.*]], label %[[FOR_INC]]
; CHECK-ZNVER4:       [[IF_THEN]]:
; CHECK-ZNVER4-NEXT:    [[SRC_PTR:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[IDX]]
; CHECK-ZNVER4-NEXT:    [[LOAD_SRC:%.*]] = load i32, ptr [[SRC_PTR]], align 4
; CHECK-ZNVER4-NEXT:    store i32 [[LOAD_SRC]], ptr [[DST_PTR]], align 4
; CHECK-ZNVER4-NEXT:    [[IDX_NEXT:%.*]] = add nsw i64 [[IDX]], 1
; CHECK-ZNVER4-NEXT:    br label %[[FOR_INC]]
; CHECK-ZNVER4:       [[FOR_INC]]:
; CHECK-ZNVER4-NEXT:    [[IDX_1]] = phi i64 [ [[IDX_NEXT]], %[[IF_THEN]] ], [ [[IDX]], %[[FOR_BODY]] ]
; CHECK-ZNVER4-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-ZNVER4-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; CHECK-ZNVER4-NEXT:    br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]]
; CHECK-ZNVER4:       [[EXIT]]:
; CHECK-ZNVER4-NEXT:    ret void
;
entry:
  br label %for.body

for.body:
  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.inc ]
  %idx = phi i64 [ 0, %entry ], [ %idx.1, %for.inc ]
  %dst.ptr = getelementptr inbounds i32, ptr %dst, i64 %iv
  %load.dst = load i32, ptr %dst.ptr, align 4
  %cmp = icmp slt i32 %load.dst, %c
  br i1 %cmp, label %if.then, label %for.inc

if.then:
  %src.ptr = getelementptr inbounds i32, ptr %src, i64 %idx
  %load.src = load i32, ptr %src.ptr, align 4
  store i32 %load.src, ptr %dst.ptr, align 4
  %idx.next = add nsw i64 %idx, 1
  br label %for.inc

for.inc:
  %idx.1 = phi i64 [ %idx.next, %if.then ], [ %idx, %for.body ]
  %iv.next = add nuw nsw i64 %iv, 1
  %exitcond.not = icmp eq i64 %iv.next, %n
  br i1 %exitcond.not, label %exit, label %for.body

exit:
  ret void
}