test/Transforms/LoopVectorize/RISCV/clmul.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -passes=loop-vectorize -mtriple=riscv64 -mattr=+v -S %s | FileCheck %s

declare i64 @llvm.clmul.i64(i64 %a, i64 %b)

define void @clmul_loop(ptr %a, ptr %b, ptr %c, i64 %n) {
; CHECK-LABEL: define void @clmul_loop(
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
; CHECK-NEXT:  [[ENTRY:.*]]:
; CHECK-NEXT:    br label %[[FOR_BODY:.*]]
; CHECK:       [[FOR_BODY]]:
; CHECK-NEXT:    [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[FOR_BODY]] ]
; CHECK-NEXT:    [[PA:%.*]] = getelementptr i64, ptr [[A]], i64 [[I]]
; CHECK-NEXT:    [[PB:%.*]] = getelementptr i64, ptr [[B]], i64 [[I]]
; CHECK-NEXT:    [[PC:%.*]] = getelementptr i64, ptr [[C]], i64 [[I]]
; CHECK-NEXT:    [[VA:%.*]] = load i64, ptr [[PA]], align 8
; CHECK-NEXT:    [[VB:%.*]] = load i64, ptr [[PB]], align 8
; CHECK-NEXT:    [[R:%.*]] = call i64 @llvm.clmul.i64(i64 [[VA]], i64 [[VB]])
; CHECK-NEXT:    store i64 [[R]], ptr [[PC]], align 8
; CHECK-NEXT:    [[I_NEXT]] = add i64 [[I]], 1
; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i64 [[I_NEXT]], [[N]]
; CHECK-NEXT:    br i1 [[CMP]], label %[[FOR_EXIT:.*]], label %[[FOR_BODY]]
; CHECK:       [[FOR_EXIT]]:
; CHECK-NEXT:    ret void
;
entry:
  br label %for.body

for.body:
  %i = phi i64 [0, %entry], [%i.next, %for.body]

  %pa = getelementptr i64, ptr %a, i64 %i
  %pb = getelementptr i64, ptr %b, i64 %i
  %pc = getelementptr i64, ptr %c, i64 %i

  %va = load i64, ptr %pa
  %vb = load i64, ptr %pb

  %r = call i64 @llvm.clmul.i64(i64 %va, i64 %vb)

  store i64 %r, ptr %pc

  %i.next = add i64 %i, 1
  %cmp = icmp eq i64 %i.next, %n
  br i1 %cmp, label %for.exit, label %for.body

for.exit:
  ret void

}