| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 |
| ; RUN: opt -S -passes=licm -verify-memoryssa < %s | FileCheck %s |
| |
| define void @test(ptr %p) { |
| ; CHECK-LABEL: define void @test( |
| ; CHECK-SAME: ptr [[P:%.*]]) { |
| ; CHECK-NEXT: [[ENTRY:.*:]] |
| ; CHECK-NEXT: br label %[[LOOP0:.*]] |
| ; CHECK: [[LOOP0]]: |
| ; CHECK-NEXT: br label %[[LOOP1:.*]] |
| ; CHECK: [[LOOP1]]: |
| ; CHECK-NEXT: [[DEC10:%.*]] = phi i64 [ 0, %[[LOOP0]] ], [ 1, %[[LOOP1]] ] |
| ; CHECK-NEXT: br i1 false, label %[[LOOP1_EXIT:.*]], label %[[LOOP1]] |
| ; CHECK: [[LOOP1_EXIT]]: |
| ; CHECK-NEXT: [[DEC10_LCSSA:%.*]] = phi i64 [ [[DEC10]], %[[LOOP1]] ] |
| ; CHECK-NEXT: switch i32 0, label %[[LOOP0_LATCH:.*]] [ |
| ; CHECK-NEXT: i32 0, label %[[LOOP0_LATCH]] |
| ; CHECK-NEXT: i32 2, label %[[LOOP3_PREHEADER:.*]] |
| ; CHECK-NEXT: i32 1, label %[[LOOP2:.*]] |
| ; CHECK-NEXT: ] |
| ; CHECK: [[LOOP2]]: |
| ; CHECK-NEXT: br i1 false, label %[[LOOP0_LATCH]], label %[[LOOP3_PREHEADER]] |
| ; CHECK: [[LOOP3_PREHEADER]]: |
| ; CHECK-NEXT: br label %[[LOOP3:.*]] |
| ; CHECK: [[LOOP3]]: |
| ; CHECK-NEXT: switch i32 0, label %[[EXIT:.*]] [ |
| ; CHECK-NEXT: i32 0, label %[[LOOP3]] |
| ; CHECK-NEXT: i32 1, label %[[LOOP2_LATCH:.*]] |
| ; CHECK-NEXT: ] |
| ; CHECK: [[LOOP2_LATCH]]: |
| ; CHECK-NEXT: br label %[[LOOP2]] |
| ; CHECK: [[LOOP0_LATCH]]: |
| ; CHECK-NEXT: br label %[[LOOP0]] |
| ; CHECK: [[EXIT]]: |
| ; CHECK-NEXT: [[DEC10_LCSSA_LCSSA:%.*]] = phi i64 [ [[DEC10_LCSSA]], %[[LOOP3]] ] |
| ; CHECK-NEXT: store i64 [[DEC10_LCSSA_LCSSA]], ptr [[P]], align 4 |
| ; CHECK-NEXT: store i64 1, ptr [[P]], align 4 |
| ; CHECK-NEXT: ret void |
| ; |
| entry: |
| br label %loop0 |
| |
| loop0: ; preds = %loop0.latch, %entry |
| br label %loop1 |
| |
| loop1: ; preds = %loop1, %loop0 |
| %dec10 = phi i64 [ 0, %loop0 ], [ 1, %loop1 ] |
| store i64 %dec10, ptr %p |
| br i1 false, label %loop1.exit, label %loop1 |
| |
| loop1.exit: ; preds = %loop1 |
| switch i32 0, label %loop0.latch [ |
| i32 0, label %loop0.latch |
| i32 2, label %loop3.preheader |
| i32 1, label %loop2 |
| ] |
| |
| loop2: ; preds = %loop2.latch, %loop1.exit |
| br i1 false, label %loop0.latch, label %loop3.preheader |
| |
| loop3.preheader: ; preds = %loop1.exit, %loop2 |
| br label %loop3 |
| |
| loop3: ; preds = %loop3.preheader, %loop3 |
| switch i32 0, label %exit [ |
| i32 0, label %loop3 |
| i32 1, label %loop2.latch |
| ] |
| |
| loop2.latch: ; preds = %loop3 |
| br label %loop2 |
| |
| loop0.latch: ; preds = %loop2, %loop1.exit, %loop1.exit |
| store i64 0, ptr %p |
| br label %loop0 |
| |
| exit: ; preds = %loop3 |
| store i64 1, ptr %p |
| ret void |
| } |
