test/Transforms/InstCombine/pr80597.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
; RUN: opt -S -passes=instcombine < %s | FileCheck %s

define i64 @pr80597(i1 %cond) {
; CHECK-LABEL: define i64 @pr80597(
; CHECK-SAME: i1 [[COND:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[ADD:%.*]] = select i1 [[COND]], i64 0, i64 -12884901888
; CHECK-NEXT:    [[SEXT1:%.*]] = add nsw i64 [[ADD]], 8836839514384105472
; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i64 [[SEXT1]], -34359738368
; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
; CHECK:       if.else:
; CHECK-NEXT:    [[SEXT2:%.*]] = ashr exact i64 [[ADD]], 1
; CHECK-NEXT:    [[ASHR:%.*]] = or disjoint i64 [[SEXT2]], 4418419761487020032
; CHECK-NEXT:    ret i64 [[ASHR]]
; CHECK:       if.then:
; CHECK-NEXT:    ret i64 0
;
entry:
  %add = select i1 %cond, i64 0, i64 4294967293
  %add8 = shl i64 %add, 32
  %sext1 = add i64 %add8, 8836839514384105472
  %cmp = icmp ult i64 %sext1, -34359738368
  br i1 %cmp, label %if.then, label %if.else

if.else:
  %sext2 = or i64 %add8, 8836839522974040064
  %ashr = ashr i64 %sext2, 1
  ret i64 %ashr

if.then:
  ret i64 0
}