test/Transforms/AtomicExpand/PowerPC/atomicrmw-fp.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -mtriple=powerpc64-unknown-unknown -passes='require<libcall-lowering-info>,atomic-expand' %s | FileCheck %s

define float @test_atomicrmw_fadd_f32(ptr %ptr, float %value) {
; CHECK-LABEL: @test_atomicrmw_fadd_f32(
; CHECK-NEXT:    call void @llvm.ppc.sync()
; CHECK-NEXT:    [[TMP6:%.*]] = load atomic i32, ptr [[PTR:%.*]] monotonic, align 4
; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[TMP6]] to float
; CHECK-NEXT:    br label [[ATOMICRMW_START:%.*]]
; CHECK:       atomicrmw.start:
; CHECK-NEXT:    [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP5:%.*]], [[CMPXCHG_END:%.*]] ]
; CHECK-NEXT:    [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
; CHECK-NEXT:    [[TMP2:%.*]] = bitcast float [[NEW]] to i32
; CHECK-NEXT:    [[TMP3:%.*]] = bitcast float [[LOADED]] to i32
; CHECK-NEXT:    br label [[CMPXCHG_START:%.*]]
; CHECK:       cmpxchg.start:
; CHECK-NEXT:    [[LARX:%.*]] = call i32 @llvm.ppc.lwarx(ptr [[PTR]])
; CHECK-NEXT:    [[SHOULD_STORE:%.*]] = icmp eq i32 [[LARX]], [[TMP3]]
; CHECK-NEXT:    br i1 [[SHOULD_STORE]], label [[CMPXCHG_FENCEDSTORE:%.*]], label [[CMPXCHG_NOSTORE:%.*]], !prof [[PROF0:![0-9]+]]
; CHECK:       cmpxchg.fencedstore:
; CHECK-NEXT:    br label [[CMPXCHG_TRYSTORE:%.*]]
; CHECK:       cmpxchg.trystore:
; CHECK-NEXT:    [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[LARX]], [[CMPXCHG_FENCEDSTORE]] ]
; CHECK-NEXT:    [[STCX:%.*]] = call i32 @llvm.ppc.stwcx(ptr [[PTR]], i32 [[TMP2]])
; CHECK-NEXT:    [[TMP4:%.*]] = xor i32 [[STCX]], 1
; CHECK-NEXT:    [[SUCCESS1:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT:    br i1 [[SUCCESS1]], label [[CMPXCHG_SUCCESS:%.*]], label [[CMPXCHG_START]], !prof [[PROF0]]
; CHECK:       cmpxchg.releasedload:
; CHECK-NEXT:    unreachable
; CHECK:       cmpxchg.success:
; CHECK-NEXT:    br label [[CMPXCHG_END]]
; CHECK:       cmpxchg.nostore:
; CHECK-NEXT:    [[LOADED_NOSTORE:%.*]] = phi i32 [ [[LARX]], [[CMPXCHG_START]] ]
; CHECK-NEXT:    br label [[CMPXCHG_FAILURE:%.*]]
; CHECK:       cmpxchg.failure:
; CHECK-NEXT:    [[LOADED_FAILURE:%.*]] = phi i32 [ [[LOADED_NOSTORE]], [[CMPXCHG_NOSTORE]] ]
; CHECK-NEXT:    br label [[CMPXCHG_END]]
; CHECK:       cmpxchg.end:
; CHECK-NEXT:    [[LOADED_EXIT:%.*]] = phi i32 [ [[LOADED_TRYSTORE]], [[CMPXCHG_SUCCESS]] ], [ [[LOADED_FAILURE]], [[CMPXCHG_FAILURE]] ]
; CHECK-NEXT:    [[SUCCESS2:%.*]] = phi i1 [ true, [[CMPXCHG_SUCCESS]] ], [ false, [[CMPXCHG_FAILURE]] ]
; CHECK-NEXT:    [[TMP5]] = bitcast i32 [[LOADED_EXIT]] to float
; CHECK-NEXT:    br i1 [[SUCCESS2]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
; CHECK:       atomicrmw.end:
; CHECK-NEXT:    call void @llvm.ppc.lwsync()
; CHECK-NEXT:    ret float [[TMP5]]
;
  %res = atomicrmw fadd ptr %ptr, float %value seq_cst
  ret float %res
}

define float @test_atomicrmw_fsub_f32(ptr %ptr, float %value) {
; CHECK-LABEL: @test_atomicrmw_fsub_f32(
; CHECK-NEXT:    call void @llvm.ppc.sync()
; CHECK-NEXT:    [[TMP6:%.*]] = load atomic i32, ptr [[PTR:%.*]] monotonic, align 4
; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[TMP6]] to float
; CHECK-NEXT:    br label [[ATOMICRMW_START:%.*]]
; CHECK:       atomicrmw.start:
; CHECK-NEXT:    [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP5:%.*]], [[CMPXCHG_END:%.*]] ]
; CHECK-NEXT:    [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]]
; CHECK-NEXT:    [[TMP2:%.*]] = bitcast float [[NEW]] to i32
; CHECK-NEXT:    [[TMP3:%.*]] = bitcast float [[LOADED]] to i32
; CHECK-NEXT:    br label [[CMPXCHG_START:%.*]]
; CHECK:       cmpxchg.start:
; CHECK-NEXT:    [[LARX:%.*]] = call i32 @llvm.ppc.lwarx(ptr [[PTR]])
; CHECK-NEXT:    [[SHOULD_STORE:%.*]] = icmp eq i32 [[LARX]], [[TMP3]]
; CHECK-NEXT:    br i1 [[SHOULD_STORE]], label [[CMPXCHG_FENCEDSTORE:%.*]], label [[CMPXCHG_NOSTORE:%.*]], !prof [[PROF0]]
; CHECK:       cmpxchg.fencedstore:
; CHECK-NEXT:    br label [[CMPXCHG_TRYSTORE:%.*]]
; CHECK:       cmpxchg.trystore:
; CHECK-NEXT:    [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[LARX]], [[CMPXCHG_FENCEDSTORE]] ]
; CHECK-NEXT:    [[STCX:%.*]] = call i32 @llvm.ppc.stwcx(ptr [[PTR]], i32 [[TMP2]])
; CHECK-NEXT:    [[TMP4:%.*]] = xor i32 [[STCX]], 1
; CHECK-NEXT:    [[SUCCESS1:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT:    br i1 [[SUCCESS1]], label [[CMPXCHG_SUCCESS:%.*]], label [[CMPXCHG_START]], !prof [[PROF0]]
; CHECK:       cmpxchg.releasedload:
; CHECK-NEXT:    unreachable
; CHECK:       cmpxchg.success:
; CHECK-NEXT:    br label [[CMPXCHG_END]]
; CHECK:       cmpxchg.nostore:
; CHECK-NEXT:    [[LOADED_NOSTORE:%.*]] = phi i32 [ [[LARX]], [[CMPXCHG_START]] ]
; CHECK-NEXT:    br label [[CMPXCHG_FAILURE:%.*]]
; CHECK:       cmpxchg.failure:
; CHECK-NEXT:    [[LOADED_FAILURE:%.*]] = phi i32 [ [[LOADED_NOSTORE]], [[CMPXCHG_NOSTORE]] ]
; CHECK-NEXT:    br label [[CMPXCHG_END]]
; CHECK:       cmpxchg.end:
; CHECK-NEXT:    [[LOADED_EXIT:%.*]] = phi i32 [ [[LOADED_TRYSTORE]], [[CMPXCHG_SUCCESS]] ], [ [[LOADED_FAILURE]], [[CMPXCHG_FAILURE]] ]
; CHECK-NEXT:    [[SUCCESS2:%.*]] = phi i1 [ true, [[CMPXCHG_SUCCESS]] ], [ false, [[CMPXCHG_FAILURE]] ]
; CHECK-NEXT:    [[TMP5]] = bitcast i32 [[LOADED_EXIT]] to float
; CHECK-NEXT:    br i1 [[SUCCESS2]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
; CHECK:       atomicrmw.end:
; CHECK-NEXT:    call void @llvm.ppc.lwsync()
; CHECK-NEXT:    ret float [[TMP5]]
;

%res = atomicrmw fsub ptr %ptr, float %value seq_cst
  ret float %res
}