test/CodeGen/Xtensa/add_shifted_imm.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s \
; RUN:   | FileCheck %s

define i64 @test_1(i32 %v) {
; CHECK-LABEL: test_1:
; CHECK:         .cfi_startproc
; CHECK-NEXT:  # %bb.0:
; CHECK-NEXT:    l32r a8, .LCPI0_0
; CHECK-NEXT:    add a2, a2, a8
; CHECK-NEXT:    movi a3, 0
; CHECK-NEXT:    ret
  %addres = add i32 %v, -65536
  %res = zext i32 %addres to i64
  ret i64 %res
}

define i64 @test_2(i32 %v) {
; CHECK-LABEL: test_2:
; CHECK:         .cfi_startproc
; CHECK-NEXT:  # %bb.0:
; CHECK-NEXT:    l32r a8, .LCPI1_0
; CHECK-NEXT:    add a2, a2, a8
; CHECK-NEXT:    movi a3, 0
; CHECK-NEXT:    ret
  %addres = add i32 %v, 65536
  %res = zext i32 %addres to i64
  ret i64 %res
}

define i64 @test_3(i32 %v) {
; CHECK-LABEL: test_3:
; CHECK:         .cfi_startproc
; CHECK-NEXT:  # %bb.0:
; CHECK-NEXT:    addmi a2, a2, -32768
; CHECK-NEXT:    movi a3, 0
; CHECK-NEXT:    ret
  %addres = add i32 %v, -32768
  %res = zext i32 %addres to i64
  ret i64 %res
}

define i64 @test_4(i32 %v) {
; CHECK-LABEL: test_4:
; CHECK:         .cfi_startproc
; CHECK-NEXT:  # %bb.0:
; CHECK-NEXT:    addmi a2, a2, 32512
; CHECK-NEXT:    movi a3, 0
; CHECK-NEXT:    ret
  %addres = add i32 %v, 32512
  %res = zext i32 %addres to i64
  ret i64 %res
}