test/CodeGen/SystemZ/twoaddr-risbg-cc-liveintervals.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z196 -run-pass=liveintervals,two-address-instruction -o - %s | FileCheck -check-prefix=Z196 %s
# RUN: llc -mtriple=s390x-linux-gnu -mcpu=zEC12 -run-pass=liveintervals,two-address-instruction -o - %s | FileCheck -check-prefix=ZEC12 %s

# Converting an AND to RISBMux or RISBGN drops the dead CC def, so the CC
# live range must be updated.

---
name:            and_32
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $r2d, $r3l

    ; Z196-LABEL: name: and_32
    ; Z196: liveins: $r2d, $r3l
    ; Z196-NEXT: {{  $}}
    ; Z196-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
    ; Z196-NEXT: [[COPY1:%[0-9]+]]:grx32bit = COPY $r3l
    ; Z196-NEXT: dead [[LOCGR:%[0-9]+]]:gr64bit = LOCGR undef [[LOCGR]], [[COPY]], 15, 8, implicit undef $cc
    ; Z196-NEXT: [[COPY2:%[0-9]+]]:gr64bit = COPY [[COPY]]
    ; Z196-NEXT: dead [[COPY2:%[0-9]+]]:gr64bit = LOCGR [[COPY2]], undef %3:gr64bit, 15, 8, implicit undef $cc
    ; Z196-NEXT: [[RISBMux:%[0-9]+]]:grx32bit = RISBMux $noreg, [[COPY1]], 31, 159, 0
    ; Z196-NEXT: $r2l = COPY [[RISBMux]]
    ; Z196-NEXT: $r3l = COPY [[COPY1]]
    ; Z196-NEXT: Return implicit $r2l, implicit $r3l
    ;
    ; ZEC12-LABEL: name: and_32
    ; ZEC12: liveins: $r2d, $r3l
    ; ZEC12-NEXT: {{  $}}
    ; ZEC12-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
    ; ZEC12-NEXT: [[COPY1:%[0-9]+]]:grx32bit = COPY $r3l
    ; ZEC12-NEXT: dead [[LOCGR:%[0-9]+]]:gr64bit = LOCGR undef [[LOCGR]], [[COPY]], 15, 8, implicit undef $cc
    ; ZEC12-NEXT: [[COPY2:%[0-9]+]]:gr64bit = COPY [[COPY]]
    ; ZEC12-NEXT: dead [[COPY2:%[0-9]+]]:gr64bit = LOCGR [[COPY2]], undef %3:gr64bit, 15, 8, implicit undef $cc
    ; ZEC12-NEXT: [[RISBMux:%[0-9]+]]:grx32bit = RISBMux $noreg, [[COPY1]], 31, 159, 0
    ; ZEC12-NEXT: $r2l = COPY [[RISBMux]]
    ; ZEC12-NEXT: $r3l = COPY [[COPY1]]
    ; ZEC12-NEXT: Return implicit $r2l, implicit $r3l
    %0:gr64bit = COPY $r2d
    %1:grx32bit = COPY $r3l
    %2:gr64bit = LOCGR %0, undef %3:gr64bit, 15, 8, implicit undef $cc
    %4:gr64bit = LOCGR undef %3, %0, 15, 8, implicit undef $cc
    %5:grx32bit = NIFMux %1, 1, implicit-def dead $cc
    $r2l = COPY %5
    $r3l = COPY %1
    Return implicit $r2l, implicit $r3l
...

---
name:            and_64
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $r2d, $r3d

    ; Z196-LABEL: name: and_64
    ; Z196: liveins: $r2d, $r3d
    ; Z196-NEXT: {{  $}}
    ; Z196-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
    ; Z196-NEXT: [[COPY1:%[0-9]+]]:gr64bit = COPY $r3d
    ; Z196-NEXT: dead [[LOCGR:%[0-9]+]]:gr64bit = LOCGR undef [[LOCGR]], [[COPY]], 15, 8, implicit undef $cc
    ; Z196-NEXT: [[COPY2:%[0-9]+]]:gr64bit = COPY [[COPY]]
    ; Z196-NEXT: dead [[COPY2:%[0-9]+]]:gr64bit = LOCGR [[COPY2]], undef %3:gr64bit, 15, 8, implicit undef $cc
    ; Z196-NEXT: [[RISBG:%[0-9]+]]:gr64bit = RISBG $noreg, [[COPY1]], 63, 175, 0, implicit-def dead $cc
    ; Z196-NEXT: $r2d = COPY [[RISBG]]
    ; Z196-NEXT: $r3d = COPY [[COPY1]]
    ; Z196-NEXT: Return implicit $r2d, implicit $r3d
    ;
    ; ZEC12-LABEL: name: and_64
    ; ZEC12: liveins: $r2d, $r3d
    ; ZEC12-NEXT: {{  $}}
    ; ZEC12-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
    ; ZEC12-NEXT: [[COPY1:%[0-9]+]]:gr64bit = COPY $r3d
    ; ZEC12-NEXT: dead [[LOCGR:%[0-9]+]]:gr64bit = LOCGR undef [[LOCGR]], [[COPY]], 15, 8, implicit undef $cc
    ; ZEC12-NEXT: [[COPY2:%[0-9]+]]:gr64bit = COPY [[COPY]]
    ; ZEC12-NEXT: dead [[COPY2:%[0-9]+]]:gr64bit = LOCGR [[COPY2]], undef %3:gr64bit, 15, 8, implicit undef $cc
    ; ZEC12-NEXT: [[RISBGN:%[0-9]+]]:gr64bit = RISBGN $noreg, [[COPY1]], 63, 175, 0
    ; ZEC12-NEXT: $r2d = COPY [[RISBGN]]
    ; ZEC12-NEXT: $r3d = COPY [[COPY1]]
    ; ZEC12-NEXT: Return implicit $r2d, implicit $r3d
    %0:gr64bit = COPY $r2d
    %1:gr64bit = COPY $r3d
    %2:gr64bit = LOCGR %0, undef %3:gr64bit, 15, 8, implicit undef $cc
    %4:gr64bit = LOCGR undef %3, %0, 15, 8, implicit undef $cc
    %5:gr64bit = NILL64 %1, 1, implicit-def dead $cc
    $r2d = COPY %5
    $r3d = COPY %1
    Return implicit $r2d, implicit $r3d
...

# Don't convert if CC is live out of the AND.
---
name:            and_32_live_cc
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $r2d, $r3l, $r4l, $r5l

    ; Z196-LABEL: name: and_32_live_cc
    ; Z196: liveins: $r2d, $r3l, $r4l, $r5l
    ; Z196-NEXT: {{  $}}
    ; Z196-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
    ; Z196-NEXT: [[COPY1:%[0-9]+]]:grx32bit = COPY $r3l
    ; Z196-NEXT: [[COPY2:%[0-9]+]]:gr32bit = COPY $r4l
    ; Z196-NEXT: [[COPY3:%[0-9]+]]:gr32bit = COPY $r5l
    ; Z196-NEXT: dead [[LOCGR:%[0-9]+]]:gr64bit = LOCGR undef [[LOCGR]], [[COPY]], 15, 8, implicit undef $cc
    ; Z196-NEXT: [[COPY4:%[0-9]+]]:gr64bit = COPY [[COPY]]
    ; Z196-NEXT: dead [[COPY4:%[0-9]+]]:gr64bit = LOCGR [[COPY4]], undef %5:gr64bit, 15, 8, implicit undef $cc
    ; Z196-NEXT: [[COPY5:%[0-9]+]]:grx32bit = COPY [[COPY1]]
    ; Z196-NEXT: [[COPY5:%[0-9]+]]:grx32bit = NIFMux [[COPY5]], 1, implicit-def $cc
    ; Z196-NEXT: [[COPY6:%[0-9]+]]:gr32bit = COPY [[COPY2]]
    ; Z196-NEXT: [[COPY6:%[0-9]+]]:gr32bit = LOCR [[COPY6]], [[COPY3]], 15, 8, implicit $cc
    ; Z196-NEXT: $r2l = COPY [[COPY5]]
    ; Z196-NEXT: $r3l = COPY [[COPY1]]
    ; Z196-NEXT: $r4l = COPY [[COPY6]]
    ; Z196-NEXT: Return implicit $r2l, implicit $r3l, implicit $r4l
    ;
    ; ZEC12-LABEL: name: and_32_live_cc
    ; ZEC12: liveins: $r2d, $r3l, $r4l, $r5l
    ; ZEC12-NEXT: {{  $}}
    ; ZEC12-NEXT: [[COPY:%[0-9]+]]:gr64bit = COPY $r2d
    ; ZEC12-NEXT: [[COPY1:%[0-9]+]]:grx32bit = COPY $r3l
    ; ZEC12-NEXT: [[COPY2:%[0-9]+]]:gr32bit = COPY $r4l
    ; ZEC12-NEXT: [[COPY3:%[0-9]+]]:gr32bit = COPY $r5l
    ; ZEC12-NEXT: dead [[LOCGR:%[0-9]+]]:gr64bit = LOCGR undef [[LOCGR]], [[COPY]], 15, 8, implicit undef $cc
    ; ZEC12-NEXT: [[COPY4:%[0-9]+]]:gr64bit = COPY [[COPY]]
    ; ZEC12-NEXT: dead [[COPY4:%[0-9]+]]:gr64bit = LOCGR [[COPY4]], undef %5:gr64bit, 15, 8, implicit undef $cc
    ; ZEC12-NEXT: [[COPY5:%[0-9]+]]:grx32bit = COPY [[COPY1]]
    ; ZEC12-NEXT: [[COPY5:%[0-9]+]]:grx32bit = NIFMux [[COPY5]], 1, implicit-def $cc
    ; ZEC12-NEXT: [[COPY6:%[0-9]+]]:gr32bit = COPY [[COPY2]]
    ; ZEC12-NEXT: [[COPY6:%[0-9]+]]:gr32bit = LOCR [[COPY6]], [[COPY3]], 15, 8, implicit $cc
    ; ZEC12-NEXT: $r2l = COPY [[COPY5]]
    ; ZEC12-NEXT: $r3l = COPY [[COPY1]]
    ; ZEC12-NEXT: $r4l = COPY [[COPY6]]
    ; ZEC12-NEXT: Return implicit $r2l, implicit $r3l, implicit $r4l
    %0:gr64bit = COPY $r2d
    %1:grx32bit = COPY $r3l
    %2:gr32bit = COPY $r4l
    %3:gr32bit = COPY $r5l
    %4:gr64bit = LOCGR %0, undef %5:gr64bit, 15, 8, implicit undef $cc
    %6:gr64bit = LOCGR undef %5, %0, 15, 8, implicit undef $cc
    %7:grx32bit = NIFMux %1, 1, implicit-def $cc
    %8:gr32bit = LOCR %2, %3, 15, 8, implicit killed $cc
    $r2l = COPY %7
    $r3l = COPY %1
    $r4l = COPY %8
    Return implicit $r2l, implicit $r3l, implicit $r4l
...