test/CodeGen/SystemZ/twoaddr-risbg-cc-liveintervals.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z196 < %s | FileCheck %s

; Converting the AND to RISBMux must remove the dead def from the CC
; live range

define i16 @and_to_risbmux_issue229045(ptr %out, ptr %in, i8 %c) {
; CHECK-LABEL: and_to_risbmux_issue229045:
; CHECK:       # %bb.0:
; CHECK-NEXT:    tmll %r4, 255
; CHECK-NEXT:    lghi %r0, 0
; CHECK-NEXT:    lghi %r1, 82
; CHECK-NEXT:    lghi %r4, 82
; CHECK-NEXT:    locgre %r1, %r0
; CHECK-NEXT:    sllg %r1, %r1, 1
; CHECK-NEXT:    lb %r1, 1(%r1,%r3)
; CHECK-NEXT:    locgre %r0, %r4
; CHECK-NEXT:    agr %r3, %r0
; CHECK-NEXT:    llc %r0, 1
; CHECK-NEXT:    stc %r1, 0(%r2)
; CHECK-NEXT:    mvc 0(1), 1(%r3)
; CHECK-NEXT:    risblg %r1, %r0, 31, 159, 0
; CHECK-NEXT:    stc %r0, 0(%r2)
; CHECK-NEXT:    lhi %r2, 0
; CHECK-NEXT:    stc %r1, 0
; CHECK-NEXT:    br %r14
  %cmp = icmp eq i8 %c, 0
  %sel0 = select i1 %cmp, i16 0, i16 82
  %ext0 = zext i16 %sel0 to i64
  %gep0 = getelementptr [2 x i8], ptr %in, i64 %ext0
  %ld0 = load i16, ptr %gep0, align 2
  %trunc0 = trunc i16 %ld0 to i8
  store i8 %trunc0, ptr %out, align 1
  %sel1 = select i1 %cmp, i64 82, i64 0
  %gep1 = getelementptr i8, ptr %in, i64 %sel1
  %ld1 = load i16, ptr %gep1, align 2
  %trunc1 = trunc i16 %ld1 to i8
  store i8 %trunc1, ptr null, align 4
  %ld2 = load i16, ptr null, align 2
  %trunc2 = trunc i16 %ld2 to i8
  %and = and i8 %trunc2, 1
  store i8 %and, ptr null, align 1
  store i8 %trunc2, ptr %out, align 2
  ret i16 0
}