test/CodeGen/SystemZ/bitcast.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=s390x-linux-gnu < %s | FileCheck -check-prefixes=CHECK,BASE %s
; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck -check-prefixes=CHECK,Z13 %s

define <2 x i64> @bitcast_fp128_to_v2i64(fp128 %arg) {
; BASE-LABEL: bitcast_fp128_to_v2i64:
; BASE:       # %bb.0:
; BASE-NEXT:    ld %f0, 0(%r2)
; BASE-NEXT:    ld %f2, 8(%r2)
; BASE-NEXT:    axbr %f0, %f0
; BASE-NEXT:    lgdr %r3, %f2
; BASE-NEXT:    lgdr %r2, %f0
; BASE-NEXT:    br %r14
;
; Z13-LABEL: bitcast_fp128_to_v2i64:
; Z13:       # %bb.0:
; Z13-NEXT:    ld %f0, 0(%r2)
; Z13-NEXT:    ld %f2, 8(%r2)
; Z13-NEXT:    axbr %f0, %f0
; Z13-NEXT:    vmrhg %v24, %v0, %v2
; Z13-NEXT:    br %r14
  %val = fadd fp128 %arg, %arg
  %cast = bitcast fp128 %val to <2 x i64>
  ret <2 x i64> %cast
}

define <4 x i32> @bitcast_fp128_to_v4i32(fp128 %arg) {
; BASE-LABEL: bitcast_fp128_to_v4i32:
; BASE:       # %bb.0:
; BASE-NEXT:    ld %f0, 0(%r2)
; BASE-NEXT:    ld %f2, 8(%r2)
; BASE-NEXT:    axbr %f0, %f0
; BASE-NEXT:    lgdr %r3, %f0
; BASE-NEXT:    lgdr %r5, %f2
; BASE-NEXT:    srlg %r2, %r3, 32
; BASE-NEXT:    srlg %r4, %r5, 32
; BASE-NEXT:    # kill: def $r2l killed $r2l killed $r2d
; BASE-NEXT:    # kill: def $r3l killed $r3l killed $r3d
; BASE-NEXT:    # kill: def $r4l killed $r4l killed $r4d
; BASE-NEXT:    # kill: def $r5l killed $r5l killed $r5d
; BASE-NEXT:    br %r14
;
; Z13-LABEL: bitcast_fp128_to_v4i32:
; Z13:       # %bb.0:
; Z13-NEXT:    ld %f0, 0(%r2)
; Z13-NEXT:    ld %f2, 8(%r2)
; Z13-NEXT:    axbr %f0, %f0
; Z13-NEXT:    vmrhg %v24, %v0, %v2
; Z13-NEXT:    br %r14
  %val = fadd fp128 %arg, %arg
  %cast = bitcast fp128 %val to <4 x i32>
  ret <4 x i32> %cast
}

define fp128 @bitcast_v2i64_to_fp128(ptr %ptr) {
; BASE-LABEL: bitcast_v2i64_to_fp128:
; BASE:       # %bb.0:
; BASE-NEXT:    lg %r1, 0(%r3)
; BASE-NEXT:    lg %r3, 8(%r3)
; BASE-NEXT:    la %r0, 0(%r1,%r1)
; BASE-NEXT:    la %r1, 0(%r3,%r3)
; BASE-NEXT:    stg %r1, 8(%r2)
; BASE-NEXT:    stg %r0, 0(%r2)
; BASE-NEXT:    br %r14
;
; Z13-LABEL: bitcast_v2i64_to_fp128:
; Z13:       # %bb.0:
; Z13-NEXT:    vl %v0, 0(%r3), 3
; Z13-NEXT:    vag %v0, %v0, %v0
; Z13-NEXT:    vst %v0, 0(%r2), 3
; Z13-NEXT:    br %r14
  %load = load <2 x i64>, ptr %ptr
  %vec = add <2 x i64> %load, %load
  %cast = bitcast <2 x i64> %vec to fp128
  ret fp128 %cast
}

define fp128 @bitcast_v4i32_to_fp128(ptr %ptr) {
; BASE-LABEL: bitcast_v4i32_to_fp128:
; BASE:       # %bb.0:
; BASE-NEXT:    l %r0, 0(%r3)
; BASE-NEXT:    l %r1, 4(%r3)
; BASE-NEXT:    l %r4, 8(%r3)
; BASE-NEXT:    l %r3, 12(%r3)
; BASE-NEXT:    ar %r0, %r0
; BASE-NEXT:    ar %r1, %r1
; BASE-NEXT:    ar %r4, %r4
; BASE-NEXT:    ar %r3, %r3
; BASE-NEXT:    st %r3, 12(%r2)
; BASE-NEXT:    st %r4, 8(%r2)
; BASE-NEXT:    st %r1, 4(%r2)
; BASE-NEXT:    st %r0, 0(%r2)
; BASE-NEXT:    br %r14
;
; Z13-LABEL: bitcast_v4i32_to_fp128:
; Z13:       # %bb.0:
; Z13-NEXT:    vl %v0, 0(%r3), 3
; Z13-NEXT:    vaf %v0, %v0, %v0
; Z13-NEXT:    vst %v0, 0(%r2), 3
; Z13-NEXT:    br %r14
  %load = load <4 x i32>, ptr %ptr
  %vec = add <4 x i32> %load, %load
  %cast = bitcast <4 x i32> %vec to fp128
  ret fp128 %cast
}

;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK: {{.*}}