test/CodeGen/RISCV/stack-offset-large.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: not llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s 2>&1 \
; RUN:   | FileCheck %s -check-prefixes=RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
; RUN:   | FileCheck %s -check-prefixes=RV64

declare void @inspect(...)

; Tests stack addressing when stack-size doesn't fit in 32bit.

; Should fail on 32-bit systems.
; RV32: LLVM ERROR: Frame offsets outside of the signed 32-bit range not supported on RV32

define void @stack_bigger_than_32bit() {
; RV64-LABEL: stack_bigger_than_32bit:
; RV64:       # %bb.0:
; RV64-NEXT:    addi sp, sp, -2032
; RV64-NEXT:    .cfi_def_cfa_offset 2032
; RV64-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
; RV64-NEXT:    .cfi_offset ra, -8
; RV64-NEXT:    lui a0, 524288
; RV64-NEXT:    addiw a0, a0, -2000
; RV64-NEXT:    sub sp, sp, a0
; RV64-NEXT:    .cfi_def_cfa_offset 2147483680
; RV64-NEXT:    li a0, 1
; RV64-NEXT:    slli a0, a0, 31
; RV64-NEXT:    addi a0, a0, 8
; RV64-NEXT:    add a0, sp, a0
; RV64-NEXT:    addi a1, sp, 8
; RV64-NEXT:    call inspect
; RV64-NEXT:    lui a0, 524288
; RV64-NEXT:    addiw a0, a0, -2000
; RV64-NEXT:    add sp, sp, a0
; RV64-NEXT:    .cfi_def_cfa_offset 2032
; RV64-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
; RV64-NEXT:    .cfi_restore ra
; RV64-NEXT:    addi sp, sp, 2032
; RV64-NEXT:    .cfi_def_cfa_offset 0
; RV64-NEXT:    ret
  %p1 = alloca [2 x i64], align 1
  %p2 = alloca [2147483648 x i8], align 1
  call void (...) @inspect(ptr %p1, ptr %p2)
  ret void
}


; Same as previous test, just uses frame-pointer to access fixed objects.
define void @vla(i64 %n) {
; RV64-LABEL: vla:
; RV64:       # %bb.0:
; RV64-NEXT:    addi sp, sp, -2032
; RV64-NEXT:    .cfi_def_cfa_offset 2032
; RV64-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
; RV64-NEXT:    sd s0, 2016(sp) # 8-byte Folded Spill
; RV64-NEXT:    .cfi_offset ra, -8
; RV64-NEXT:    .cfi_offset s0, -16
; RV64-NEXT:    addi s0, sp, 2032
; RV64-NEXT:    .cfi_def_cfa s0, 0
; RV64-NEXT:    lui a1, 524288
; RV64-NEXT:    addiw a1, a1, -1984
; RV64-NEXT:    sub sp, sp, a1
; RV64-NEXT:    slli a0, a0, 2
; RV64-NEXT:    addi a0, a0, 15
; RV64-NEXT:    andi a0, a0, -16
; RV64-NEXT:    sub a2, sp, a0
; RV64-NEXT:    mv sp, a2
; RV64-NEXT:    addi a0, s0, -40
; RV64-NEXT:    li a1, 1
; RV64-NEXT:    slli a1, a1, 31
; RV64-NEXT:    addi a1, a1, 40
; RV64-NEXT:    sub a1, s0, a1
; RV64-NEXT:    call inspect
; RV64-NEXT:    addi sp, s0, -2032
; RV64-NEXT:    .cfi_def_cfa sp, 2032
; RV64-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
; RV64-NEXT:    ld s0, 2016(sp) # 8-byte Folded Reload
; RV64-NEXT:    .cfi_restore ra
; RV64-NEXT:    .cfi_restore s0
; RV64-NEXT:    addi sp, sp, 2032
; RV64-NEXT:    .cfi_def_cfa_offset 0
; RV64-NEXT:    ret
  %p1 = alloca [2 x i64], align 1
  %p2 = alloca [2147483648 x i8], align 1
  %vla = alloca i32, i64 %n, align 4
  call void (...) @inspect(ptr %p1, ptr %p2, ptr %vla)
  ret void
}

define void @rvv_frame_obj() {
; RV64-LABEL: rvv_frame_obj:
; RV64:       # %bb.0:
; RV64-NEXT:    addi sp, sp, -2032
; RV64-NEXT:    .cfi_def_cfa_offset 2032
; RV64-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
; RV64-NEXT:    .cfi_offset ra, -8
; RV64-NEXT:    lui a0, 524288
; RV64-NEXT:    addiw a0, a0, -1984
; RV64-NEXT:    sub sp, sp, a0
; RV64-NEXT:    .cfi_def_cfa_offset 2147483696
; RV64-NEXT:    csrr a0, vlenb
; RV64-NEXT:    slli a0, a0, 1
; RV64-NEXT:    sub sp, sp, a0
; RV64-NEXT:    .cfi_escape 0x0f, 0x11, 0x72, 0x00, 0x11, 0xb0, 0x80, 0x80, 0x80, 0x08, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 2147483696 + 2 * vlenb
; RV64-NEXT:    li a0, 1
; RV64-NEXT:    slli a0, a0, 31
; RV64-NEXT:    addi a0, a0, 8
; RV64-NEXT:    add a0, sp, a0
; RV64-NEXT:    addi a1, sp, 8
; RV64-NEXT:    csrr a2, vlenb
; RV64-NEXT:    add a2, sp, a2
; RV64-NEXT:    li a3, 1
; RV64-NEXT:    slli a3, a3, 31
; RV64-NEXT:    addi a3, a3, 32
; RV64-NEXT:    add a2, a2, a3
; RV64-NEXT:    li a3, 1
; RV64-NEXT:    slli a3, a3, 31
; RV64-NEXT:    addi a3, a3, 32
; RV64-NEXT:    add a3, sp, a3
; RV64-NEXT:    call inspect
; RV64-NEXT:    csrr a0, vlenb
; RV64-NEXT:    slli a0, a0, 1
; RV64-NEXT:    add sp, sp, a0
; RV64-NEXT:    .cfi_def_cfa sp, 2032
; RV64-NEXT:    lui a0, 524288
; RV64-NEXT:    addiw a0, a0, -1984
; RV64-NEXT:    add sp, sp, a0
; RV64-NEXT:    .cfi_def_cfa_offset 2032
; RV64-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
; RV64-NEXT:    .cfi_restore ra
; RV64-NEXT:    addi sp, sp, 2032
; RV64-NEXT:    .cfi_def_cfa_offset 0
; RV64-NEXT:    ret
  %p1 = alloca [2 x i64], align 1
  %p2 = alloca [2147483648 x i8], align 1
  %vector1 = alloca <vscale x 1 x i64>, align 1
  %vector2 = alloca <vscale x 1 x i64>, align 1
  call void (...) @inspect(ptr %p1, ptr %p2, ptr %vector1, ptr %vector2)
  ret void
}

define <vscale x 1 x i64> @rvv_spill(<vscale x 1 x i64> %vector) {
; RV64-LABEL: rvv_spill:
; RV64:       # %bb.0:
; RV64-NEXT:    addi sp, sp, -2032
; RV64-NEXT:    .cfi_def_cfa_offset 2032
; RV64-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
; RV64-NEXT:    .cfi_offset ra, -8
; RV64-NEXT:    lui a0, 524288
; RV64-NEXT:    addiw a0, a0, -1968
; RV64-NEXT:    sub sp, sp, a0
; RV64-NEXT:    .cfi_def_cfa_offset 2147483712
; RV64-NEXT:    csrr a0, vlenb
; RV64-NEXT:    sub sp, sp, a0
; RV64-NEXT:    .cfi_escape 0x0f, 0x11, 0x72, 0x00, 0x11, 0xc0, 0x80, 0x80, 0x80, 0x08, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 2147483712 + 1 * vlenb
; RV64-NEXT:    li a0, 1
; RV64-NEXT:    slli a0, a0, 31
; RV64-NEXT:    addi a0, a0, 48
; RV64-NEXT:    add a0, sp, a0
; RV64-NEXT:    vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
; RV64-NEXT:    #APP
; RV64-NEXT:    #NO_APP
; RV64-NEXT:    li a0, 1
; RV64-NEXT:    slli a0, a0, 31
; RV64-NEXT:    addi a0, a0, 24
; RV64-NEXT:    add a0, sp, a0
; RV64-NEXT:    addi a1, sp, 24
; RV64-NEXT:    call inspect
; RV64-NEXT:    li a0, 1
; RV64-NEXT:    slli a0, a0, 31
; RV64-NEXT:    addi a0, a0, 48
; RV64-NEXT:    add a0, sp, a0
; RV64-NEXT:    vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT:    csrr a0, vlenb
; RV64-NEXT:    add sp, sp, a0
; RV64-NEXT:    .cfi_def_cfa sp, 2032
; RV64-NEXT:    lui a0, 524288
; RV64-NEXT:    addiw a0, a0, -1968
; RV64-NEXT:    add sp, sp, a0
; RV64-NEXT:    .cfi_def_cfa_offset 2032
; RV64-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
; RV64-NEXT:    .cfi_restore ra
; RV64-NEXT:    addi sp, sp, 2032
; RV64-NEXT:    .cfi_def_cfa_offset 0
; RV64-NEXT:    ret
  call void asm sideeffect "",
  "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()

  %p1 = alloca [2 x i64], align 1
  %p2 = alloca [2147483648 x i8], align 1
  call void (...) @inspect(ptr %p1, ptr %p2)
  ret <vscale x 1 x i64> %vector
}