test/CodeGen/RISCV/select-pseudo-merge-with-stack-adj.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc %s -mtriple riscv32 -verify-machineinstrs -o - | FileCheck %s

define i32 @test(i1 %arg_1, i32 %arg_2) {
; CHECK-LABEL: test:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    addi sp, sp, -16
; CHECK-NEXT:    .cfi_def_cfa_offset 16
; CHECK-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
; CHECK-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
; CHECK-NEXT:    .cfi_offset ra, -4
; CHECK-NEXT:    .cfi_offset s0, -8
; CHECK-NEXT:    .cfi_offset s1, -12
; CHECK-NEXT:    andi s1, a0, 1
; CHECK-NEXT:    mv a0, a1
; CHECK-NEXT:    mv s0, a1
; CHECK-NEXT:    bnez s1, .LBB0_2
; CHECK-NEXT:  # %bb.1: # %entry
; CHECK-NEXT:    li s0, 1
; CHECK-NEXT:  .LBB0_2: # %entry
; CHECK-NEXT:    li a1, 7
; CHECK-NEXT:    call __udivsi3
; CHECK-NEXT:    bnez s1, .LBB0_4
; CHECK-NEXT:  # %bb.3: # %entry
; CHECK-NEXT:    li a0, 3
; CHECK-NEXT:  .LBB0_4: # %entry
; CHECK-NEXT:    bnez s1, .LBB0_6
; CHECK-NEXT:  # %bb.5: # %entry
; CHECK-NEXT:    mv s0, a0
; CHECK-NEXT:  .LBB0_6: # %entry
; CHECK-NEXT:    li a0, 3
; CHECK-NEXT:  .LBB0_7: # %body
; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
; CHECK-NEXT:    addi s0, s0, 4
; CHECK-NEXT:    bltu a0, s0, .LBB0_7
; CHECK-NEXT:  # %bb.8: # %exit
; CHECK-NEXT:    mv a0, s0
; CHECK-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
; CHECK-NEXT:    .cfi_restore ra
; CHECK-NEXT:    .cfi_restore s0
; CHECK-NEXT:    .cfi_restore s1
; CHECK-NEXT:    addi sp, sp, 16
; CHECK-NEXT:    .cfi_def_cfa_offset 0
; CHECK-NEXT:    ret
entry:
  %sel_1 = select i1 %arg_1, i32 %arg_2, i32 1
  %div = udiv i32 %arg_2, 7
  %cond_1 = icmp ugt i32 %div, %sel_1
  %sel_2 = select i1 %arg_1, i32 %div, i32 3
  %sel = select i1 %arg_1, i32 %sel_1, i32 %sel_2
  br label %body

body:
  %res = phi i32 [ %sel, %entry ], [ %add_loop, %body ]
  %add_loop = add i32 4, %res
  %cond_2 = icmp ugt i32 %add_loop, 3
  br i1 %cond_2, label %body, label %exit

exit:
  ret i32 %add_loop
}