test/CodeGen/RISCV/pr94265.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32-- -mattr=+v | FileCheck -check-prefix=RV32I %s
; RUN: llc < %s -mtriple=riscv64-- -mattr=+v | FileCheck -check-prefix=RV64I %s
; RUN: llc < %s -mtriple=riscv32-- -mattr=+zve32x,+zvl128b | FileCheck -check-prefix=RV32I %s
; RUN: llc < %s -mtriple=riscv64-- -mattr=+zve32x,+zvl128b | FileCheck -check-prefix=RV64I %s

define <8 x i16> @PR94265(<8 x i32> %a0) #0 {
; RV32I-LABEL: PR94265:
; RV32I:       # %bb.0:
; RV32I-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; RV32I-NEXT:    vsra.vi v10, v8, 31
; RV32I-NEXT:    vsrl.vi v10, v10, 26
; RV32I-NEXT:    vadd.vv v8, v8, v10
; RV32I-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; RV32I-NEXT:    vnsrl.wi v10, v8, 6
; RV32I-NEXT:    vsll.vi v8, v10, 10
; RV32I-NEXT:    ret
;
; RV64I-LABEL: PR94265:
; RV64I:       # %bb.0:
; RV64I-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; RV64I-NEXT:    vsra.vi v10, v8, 31
; RV64I-NEXT:    vsrl.vi v10, v10, 26
; RV64I-NEXT:    vadd.vv v8, v8, v10
; RV64I-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; RV64I-NEXT:    vnsrl.wi v10, v8, 6
; RV64I-NEXT:    vsll.vi v8, v10, 10
; RV64I-NEXT:    ret
  %t1 = sdiv <8 x i32> %a0, <i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64>
  %t2 = trunc <8 x i32> %t1 to <8 x i16>
  %t3 = shl <8 x i16> %t2, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
  ret <8 x i16> %t3
}