test/CodeGen/RISCV/branch-rel.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc %s -mtriple=riscv64 -run-pass=branch-relaxation -o - -verify-machineinstrs | FileCheck %s

--- |
  define void @foo() {
    ret void
  }
...
---
name:            foo
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: foo
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT:   liveins: $x1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   PseudoBR %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT:   liveins: $x1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   INLINEASM &".space 4096", 1 /* sideeffect attdialect */
  ; CHECK-NEXT:   BGE $x1, $x0, %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   PseudoRET
  bb.0:
    liveins: $x1
    BNE $x1, $x0, %bb.3
    PseudoBR %bb.3
  bb.1:
    liveins: $x1
    INLINEASM &".space 4096", 1
    BGE $x1, $x0, %bb.3
  bb.3:
    PseudoRET
## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: