test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/inline-memset.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=mips-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
  target datalayout = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
  target triple = "mipsel-pc-linux-gnu"

  declare void @llvm.memset.inline.p0.i64(ptr noalias nocapture writeonly, i8, i64 immarg, i1 immarg) #0

  define void @test_memset_inline(ptr nocapture %dst, i8 %val) local_unnamed_addr {
  entry:
    tail call void @llvm.memset.inline.p0.i64(ptr align 4 %dst, i8 %val, i64 2, i1 false)
    ret void
  }

  attributes #0 = { argmemonly nofree nounwind willreturn }

...
---
name:            test_memset_inline
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
liveins:
  - { reg: '$a0' }
  - { reg: '$a1' }
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; MIPS32-LABEL: name: test_memset_inline
    ; MIPS32: liveins: $a0, $a1
    ; MIPS32-NEXT: {{  $}}
    ; MIPS32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
    ; MIPS32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
    ; MIPS32-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
    ; MIPS32-NEXT: G_STORE [[TRUNC]](s8), [[COPY]](p0) :: (store (s8) into %ir.dst, align 4)
    ; MIPS32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; MIPS32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s32)
    ; MIPS32-NEXT: G_STORE [[TRUNC]](s8), [[PTR_ADD]](p0) :: (store (s8) into %ir.dst + 1, basealign 4)
    ; MIPS32-NEXT: RetRA
    %0:_(p0) = COPY $a0
    %1:_(s32) = COPY $a1
    %2:_(s8) = G_TRUNC %1(s32)
    %3:_(s64) = G_CONSTANT i64 2
    %4:_(s32) = G_TRUNC %3(s64)
    G_MEMSET_INLINE %0(p0), %2(s8), %4(s32) :: (store (s8) into %ir.dst, align 4)
    RetRA

...