test/CodeGen/ARM/stlf-vector-extract.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=armeb-eabi -mattr=+v7,+neon | FileCheck %s --check-prefix=BE
; RUN: llc < %s -mtriple=arm-eabi -mattr=+v7,+neon | FileCheck %s --check-prefix=LE

define <2 x i32> @test_offset_load(ptr %p, <4 x i32> %v) {
; BE-LABEL: test_offset_load:
; BE:       @ %bb.0:
; BE-NEXT:    vldr d17, [sp]
; BE-NEXT:    vmov r1, r12, d17
; BE-NEXT:    vmov d16, r3, r2
; BE-NEXT:    vst1.64 {d16, d17}, [r0:128]
; BE-NEXT:    mov r0, r12
; BE-NEXT:    bx lr
;
; LE-LABEL: test_offset_load:
; LE:       @ %bb.0:
; LE-NEXT:    vldr d17, [sp]
; LE-NEXT:    mov r1, #8
; LE-NEXT:    vmov d16, r2, r3
; LE-NEXT:    vst1.32 {d16, d17}, [r0:128], r1
; LE-NEXT:    vldr d16, [r0]
; LE-NEXT:    vmov r0, r1, d16
; LE-NEXT:    bx lr
  store <4 x i32> %v, ptr %p, align 16
  %p2 = getelementptr i8, ptr %p, i64 8
  %res = load <2 x i32>, ptr %p2, align 8
  ret <2 x i32> %res
}