test/CodeGen/ARM/abdu.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=armv7a-eabihf | FileCheck %s --check-prefixes=ARM
; RUN: llc < %s -mtriple=thumbv7m-eabi | FileCheck %s --check-prefixes=THUMB

; l < 2^31 <= r, so abdu(l, r) == r - l: should not become abs(sub).
define i32 @abd_select_known_order_i32(i32 %a, i32 %b) nounwind {
; ARM-LABEL: abd_select_known_order_i32:
; ARM:       @ %bb.0:
; ARM-NEXT:    orr r1, r1, #-2147483648
; ARM-NEXT:    sub r0, r1, r0, lsr #1
; ARM-NEXT:    bx lr
;
; THUMB-LABEL: abd_select_known_order_i32:
; THUMB:       @ %bb.0:
; THUMB-NEXT:    orr r1, r1, #-2147483648
; THUMB-NEXT:    sub.w r0, r1, r0, lsr #1
; THUMB-NEXT:    bx lr
  %l = lshr i32 %a, 1
  %r = or i32 %b, -2147483648
  %c = icmp ugt i32 %l, %r
  %s1 = sub i32 %l, %r
  %s2 = sub i32 %r, %l
  %res = select i1 %c, i32 %s1, i32 %s2
  ret i32 %res
}