test/CodeGen/AMDGPU/wmma-scale-src-perm.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgpu12.50 -O3 < %s | FileCheck %s

define amdgpu_ps <8 x float> @wmma_scale_src_uniform_pack(<16 x i32> %a, <16 x i32> %b, <8 x float> %c, i32 inreg %scale0, i32 inreg %scale1) {
; CHECK-LABEL: wmma_scale_src_uniform_pack:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; CHECK-NEXT:    s_mov_b64 s[64:65], 0
; CHECK-NEXT:    v_nop
; CHECK-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; CHECK-NEXT:    v_perm_b32 v40, s0, s1, 4
; CHECK-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(TRANS32_DEP_1)
; CHECK-NEXT:    v_wmma_scale_f32_16x16x128_f8f6f4 v[32:39], v[0:15], v[16:31], v[32:39], v40, v40 matrix_a_fmt:MATRIX_FMT_BF8 matrix_b_fmt:MATRIX_FMT_BF8
; CHECK-NEXT:    v_nop
; CHECK-NEXT:    v_nop
; CHECK-NEXT:    v_nop
; CHECK-NEXT:    v_nop
; CHECK-NEXT:    v_dual_mov_b32 v0, v32 :: v_dual_mov_b32 v1, v33
; CHECK-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; CHECK-NEXT:    v_dual_mov_b32 v2, v34 :: v_dual_mov_b32 v3, v35
; CHECK-NEXT:    v_dual_mov_b32 v4, v36 :: v_dual_mov_b32 v5, v37
; CHECK-NEXT:    v_dual_mov_b32 v6, v38 :: v_dual_mov_b32 v7, v39
; CHECK-NEXT:    ; return to shader part epilog
  %byte0 = and i32 %scale0, 255
  %byte1 = and i32 %scale1, 255
  %byte1.shift8 = shl i32 %byte1, 8
  %byte1.shift16 = shl i32 %byte1, 16
  %byte1.shift24 = shl i32 %byte1, 24
  %pack01 = or i32 %byte0, %byte1.shift8
  %pack23 = or i32 %byte1.shift16, %byte1.shift24
  %pack = or i32 %pack01, %pack23
  %res = call <8 x float> @llvm.amdgcn.wmma.scale.f32.16x16x128.f8f6f4.v8f32.v16i32.v16i32(i32 1, <16 x i32> %a, i32 1, <16 x i32> %b, i16 0, <8 x float> %c, i32 0, i32 0, i32 %pack, i32 0, i32 0, i32 %pack, i1 false, i1 false)
  ret <8 x float> %res
}

define amdgpu_ps void @uniform_pack_not_wmma_scale(i32 inreg %scale0, i32 inreg %scale1) {
; CHECK-LABEL: uniform_pack_not_wmma_scale:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; CHECK-NEXT:    s_mov_b64 s[64:65], 0
; CHECK-NEXT:    v_nop
; CHECK-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; CHECK-NEXT:    v_perm_b32 v0, s0, s1, 4
; CHECK-NEXT:    ;;#ASMSTART
; CHECK-NEXT:    ; use v0
; CHECK-NEXT:    ;;#ASMEND
; CHECK-NEXT:    s_endpgm
  %byte0 = and i32 %scale0, 255
  %byte1 = and i32 %scale1, 255
  %byte1.shift8 = shl i32 %byte1, 8
  %byte1.shift16 = shl i32 %byte1, 16
  %byte1.shift24 = shl i32 %byte1, 24
  %pack01 = or i32 %byte0, %byte1.shift8
  %pack23 = or i32 %byte1.shift16, %byte1.shift24
  %pack = or i32 %pack01, %pack23
  call void asm sideeffect "; use $0", "s"(i32 %pack)
  ret void
}

define amdgpu_ps <8 x float> @wmma_scale_src_extra_use(<16 x i32> %a, <16 x i32> %b, <8 x float> %c, i32 inreg %scale0, i32 inreg %scale1) {
; CHECK-LABEL: wmma_scale_src_extra_use:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; CHECK-NEXT:    s_mov_b64 s[64:65], 0
; CHECK-NEXT:    v_nop
; CHECK-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; CHECK-NEXT:    v_perm_b32 v40, s0, s1, 4
; CHECK-NEXT:    ;;#ASMSTART
; CHECK-NEXT:    ; use v40
; CHECK-NEXT:    ;;#ASMEND
; CHECK-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(TRANS32_DEP_1)
; CHECK-NEXT:    v_wmma_scale_f32_16x16x128_f8f6f4 v[32:39], v[0:15], v[16:31], v[32:39], v40, v40 matrix_a_fmt:MATRIX_FMT_BF8 matrix_b_fmt:MATRIX_FMT_BF8
; CHECK-NEXT:    v_nop
; CHECK-NEXT:    v_nop
; CHECK-NEXT:    v_nop
; CHECK-NEXT:    v_nop
; CHECK-NEXT:    v_dual_mov_b32 v0, v32 :: v_dual_mov_b32 v1, v33
; CHECK-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; CHECK-NEXT:    v_dual_mov_b32 v2, v34 :: v_dual_mov_b32 v3, v35
; CHECK-NEXT:    v_dual_mov_b32 v4, v36 :: v_dual_mov_b32 v5, v37
; CHECK-NEXT:    v_dual_mov_b32 v6, v38 :: v_dual_mov_b32 v7, v39
; CHECK-NEXT:    ; return to shader part epilog
  %byte0 = and i32 %scale0, 255
  %byte1 = and i32 %scale1, 255
  %byte1.shift8 = shl i32 %byte1, 8
  %byte1.shift16 = shl i32 %byte1, 16
  %byte1.shift24 = shl i32 %byte1, 24
  %pack01 = or i32 %byte0, %byte1.shift8
  %pack23 = or i32 %byte1.shift16, %byte1.shift24
  %pack = or i32 %pack01, %pack23
  call void asm sideeffect "; use $0", "s"(i32 %pack)
  %res = call <8 x float> @llvm.amdgcn.wmma.scale.f32.16x16x128.f8f6f4.v8f32.v16i32.v16i32(i32 1, <16 x i32> %a, i32 1, <16 x i32> %b, i16 0, <8 x float> %c, i32 0, i32 0, i32 %pack, i32 0, i32 0, i32 %pack, i1 false, i1 false)
  ret <8 x float> %res
}

declare <8 x float> @llvm.amdgcn.wmma.scale.f32.16x16x128.f8f6f4.v8f32.v16i32.v16i32(i32 immarg, <16 x i32>, i32 immarg, <16 x i32>, i16 immarg, <8 x float>, i32 immarg, i32 immarg, i32, i32 immarg, i32 immarg, i32, i1 immarg, i1 immarg)