test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefixes=GCN %s

---
name:            mask_hazard_cndmask_t16_dpp4
body:            |
  bb.0:
    ; GCN-LABEL: name: mask_hazard_cndmask_t16_dpp4
    ; GCN: $vgpr0_lo16 = V_CNDMASK_B16_t16_e64_dpp $vgpr0_lo16, 0, $vgpr1_lo16, 0, $vgpr2_lo16, $sgpr2_sgpr3, 0, 1, 15, 15, 1, implicit $exec
    ; GCN-NEXT: $sgpr2_sgpr3 = S_CSELECT_B64 -1, 0, implicit $scc
    ; GCN-NEXT: S_WAITCNT_DEPCTR 65534
    ; GCN-NEXT: S_ENDPGM 0
    $vgpr0_lo16 = V_CNDMASK_B16_t16_e64_dpp $vgpr0_lo16, 0, $vgpr1_lo16, 0, $vgpr2_lo16, $sgpr2_sgpr3, 0, 1, 15, 15, 1, implicit $exec
    $sgpr2_sgpr3 = S_CSELECT_B64 -1, 0, implicit $scc
    S_ENDPGM 0
...