test/CodeGen/AMDGPU/s-barrier-array-index.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel=0 -mtriple=amdgpu12.50-amd-amdhsa < %s | FileCheck -check-prefix=SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu12.50-amd-amdhsa < %s | FileCheck -check-prefix=GISEL %s

; @bars is assigned barrier ID 1, so &bars[i] must select barrier ID 1 + i.

@bars = internal addrspace(15) global [4 x target("amdgcn.named.barrier", 0)] poison

define amdgpu_kernel void @signal_var_const_idx() {
; SDAG-LABEL: signal_var_const_idx:
; SDAG:       ; %bb.0:
; SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; SDAG-NEXT:    s_mov_b64 s[64:65], 0
; SDAG-NEXT:    v_nop
; SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; SDAG-NEXT:    s_mov_b32 m0, 3
; SDAG-NEXT:    s_barrier_signal m0
; SDAG-NEXT:    s_endpgm
;
; GISEL-LABEL: signal_var_const_idx:
; GISEL:       ; %bb.0:
; GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GISEL-NEXT:    v_nop
; GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GISEL-NEXT:    s_barrier_signal 3
; GISEL-NEXT:    s_endpgm
  %bar = getelementptr [4 x target("amdgcn.named.barrier", 0)], ptr addrspace(15) @bars, i32 0, i32 2
  call void @llvm.amdgcn.s.barrier.signal.var(ptr addrspace(15) %bar, i32 0)
  ret void
}

define amdgpu_kernel void @init_dynamic_idx(i32 %idx, i32 %cnt) {
; SDAG-LABEL: init_dynamic_idx:
; SDAG:       ; %bb.0:
; SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; SDAG-NEXT:    s_mov_b64 s[64:65], 0
; SDAG-NEXT:    v_nop
; SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; SDAG-NEXT:    s_wait_kmcnt 0x0
; SDAG-NEXT:    s_add_co_i32 s0, s0, 1
; SDAG-NEXT:    s_and_b32 s1, s1, 63
; SDAG-NEXT:    s_and_b32 s0, s0, 63
; SDAG-NEXT:    s_lshl_b32 s1, s1, 16
; SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-NEXT:    s_or_b32 m0, s1, s0
; SDAG-NEXT:    s_barrier_init m0
; SDAG-NEXT:    s_endpgm
;
; GISEL-LABEL: init_dynamic_idx:
; GISEL:       ; %bb.0:
; GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GISEL-NEXT:    v_nop
; GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0 nv
; GISEL-NEXT:    s_wait_kmcnt 0x0
; GISEL-NEXT:    s_add_co_u32 s0, 1, s0
; GISEL-NEXT:    s_and_b32 s1, s1, 63
; GISEL-NEXT:    s_and_b32 s0, s0, 63
; GISEL-NEXT:    s_lshl_b32 s1, s1, 16
; GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-NEXT:    s_or_b32 m0, s0, s1
; GISEL-NEXT:    s_barrier_init m0
; GISEL-NEXT:    s_endpgm
  %bar = getelementptr [4 x target("amdgcn.named.barrier", 0)], ptr addrspace(15) @bars, i32 0, i32 %idx
  call void @llvm.amdgcn.s.barrier.init(ptr addrspace(15) %bar, i32 %cnt)
  ret void
}

define amdgpu_kernel void @join_dynamic_idx(i32 %idx) {
; SDAG-LABEL: join_dynamic_idx:
; SDAG:       ; %bb.0:
; SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; SDAG-NEXT:    s_mov_b64 s[64:65], 0
; SDAG-NEXT:    v_nop
; SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; SDAG-NEXT:    s_load_b32 s0, s[4:5], 0x0 nv
; SDAG-NEXT:    s_wait_kmcnt 0x0
; SDAG-NEXT:    s_add_co_i32 s0, s0, 1
; SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; SDAG-NEXT:    s_and_b32 m0, s0, 63
; SDAG-NEXT:    s_barrier_join m0
; SDAG-NEXT:    s_endpgm
;
; GISEL-LABEL: join_dynamic_idx:
; GISEL:       ; %bb.0:
; GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GISEL-NEXT:    v_nop
; GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GISEL-NEXT:    s_load_b32 s0, s[4:5], 0x0 nv
; GISEL-NEXT:    s_wait_kmcnt 0x0
; GISEL-NEXT:    s_add_co_u32 s0, 1, s0
; GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GISEL-NEXT:    s_and_b32 m0, s0, 63
; GISEL-NEXT:    s_barrier_join m0
; GISEL-NEXT:    s_endpgm
  %bar = getelementptr [4 x target("amdgcn.named.barrier", 0)], ptr addrspace(15) @bars, i32 0, i32 %idx
  call void @llvm.amdgcn.s.barrier.join(ptr addrspace(15) %bar)
  ret void
}

define amdgpu_kernel void @get_state_dynamic_idx(ptr addrspace(1) %out, i32 %idx) {
; SDAG-LABEL: get_state_dynamic_idx:
; SDAG:       ; %bb.0:
; SDAG-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; SDAG-NEXT:    s_mov_b64 s[64:65], 0
; SDAG-NEXT:    v_nop
; SDAG-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; SDAG-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0 nv
; SDAG-NEXT:    s_wait_kmcnt 0x0
; SDAG-NEXT:    s_add_co_i32 s2, s2, 1
; SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_2)
; SDAG-NEXT:    s_and_b32 m0, s2, 63
; SDAG-NEXT:    s_get_barrier_state s2, m0
; SDAG-NEXT:    s_wait_kmcnt 0x0
; SDAG-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; SDAG-NEXT:    global_store_b32 v0, v1, s[0:1]
; SDAG-NEXT:    s_endpgm
;
; GISEL-LABEL: get_state_dynamic_idx:
; GISEL:       ; %bb.0:
; GISEL-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-NEXT:    s_mov_b64 s[64:65], 0
; GISEL-NEXT:    v_nop
; GISEL-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GISEL-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0 nv
; GISEL-NEXT:    v_mov_b32_e32 v1, 0
; GISEL-NEXT:    s_wait_kmcnt 0x0
; GISEL-NEXT:    s_add_co_u32 s2, 1, s2
; GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_2)
; GISEL-NEXT:    s_and_b32 m0, s2, 63
; GISEL-NEXT:    s_get_barrier_state s2, m0
; GISEL-NEXT:    s_wait_kmcnt 0x0
; GISEL-NEXT:    v_mov_b32_e32 v0, s2
; GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
; GISEL-NEXT:    s_endpgm
  %bar = getelementptr [4 x target("amdgcn.named.barrier", 0)], ptr addrspace(15) @bars, i32 0, i32 %idx
  %state = call i32 @llvm.amdgcn.s.get.named.barrier.state(ptr addrspace(15) %bar)
  store i32 %state, ptr addrspace(1) %out
  ret void
}