test/CodeGen/AMDGPU/optimize-compare-cselect-debug.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgpu9.00 -run-pass=peephole-opt -o - %s | FileCheck %s

# Nine DBG_VALUEs make the raw scan exceed ScanLimit before it reaches the
# following SCC definition. Debug instructions must not consume that budget.

--- |
  define amdgpu_cs void @invert_scc_scan_budget() !dbg !3 {
    ret void
  }

  !llvm.dbg.cu = !{!0}
  !llvm.module.flags = !{!2}
  !0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
  !1 = !DIFile(filename: "invert-scc-scan-budget.c", directory: "/")
  !2 = !{i32 2, !"Debug Info Version", i32 3}
  !3 = distinct !DISubprogram(name: "invert_scc_scan_budget", scope: !1, file: !1, line: 1, type: !4, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !{!5})
  !4 = !DISubroutineType(types: !{})
  !5 = !DILocalVariable(name: "value", scope: !3, file: !1, line: 1, type: !6)
  !6 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
  !7 = !DILocation(line: 1, column: 1, scope: !3)
...
---
name: invert_scc_scan_budget
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: invert_scc_scan_budget
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 $sgpr0, 1, implicit-def $scc
    ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 9
    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 7
    ; CHECK-NEXT: DBG_VALUE [[S_ADD_U32_]], $noreg, !7, !DIExpression(), debug-location !DILocation(line: 1, column: 1, scope: !3)
    ; CHECK-NEXT: DBG_VALUE [[S_ADD_U32_]], $noreg, !7, !DIExpression(), debug-location !DILocation(line: 1, column: 1, scope: !3)
    ; CHECK-NEXT: DBG_VALUE [[S_ADD_U32_]], $noreg, !7, !DIExpression(), debug-location !DILocation(line: 1, column: 1, scope: !3)
    ; CHECK-NEXT: DBG_VALUE [[S_ADD_U32_]], $noreg, !7, !DIExpression(), debug-location !DILocation(line: 1, column: 1, scope: !3)
    ; CHECK-NEXT: DBG_VALUE [[S_ADD_U32_]], $noreg, !7, !DIExpression(), debug-location !DILocation(line: 1, column: 1, scope: !3)
    ; CHECK-NEXT: DBG_VALUE [[S_ADD_U32_]], $noreg, !7, !DIExpression(), debug-location !DILocation(line: 1, column: 1, scope: !3)
    ; CHECK-NEXT: DBG_VALUE [[S_ADD_U32_]], $noreg, !7, !DIExpression(), debug-location !DILocation(line: 1, column: 1, scope: !3)
    ; CHECK-NEXT: DBG_VALUE [[S_ADD_U32_]], $noreg, !7, !DIExpression(), debug-location !DILocation(line: 1, column: 1, scope: !3)
    ; CHECK-NEXT: DBG_VALUE [[S_ADD_U32_]], $noreg, !7, !DIExpression(), debug-location !DILocation(line: 1, column: 1, scope: !3)
    ; CHECK-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 killed [[S_MOV_B32_]], killed [[S_MOV_B32_1]], implicit $scc
    ; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_ADD_U32_]], killed [[S_CSELECT_B32_]], implicit-def dead $scc
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_ADD_I32_]]
    %0:sreg_32 = S_ADD_I32 $sgpr0, 1, implicit-def dead $scc
    S_CMP_LG_U32 %0, 0, implicit-def $scc
    %1:sreg_32 = S_MOV_B32 9
    %2:sreg_32 = S_MOV_B32 7
    DBG_VALUE %0, $noreg, !5, !DIExpression(), debug-location !7
    DBG_VALUE %0, $noreg, !5, !DIExpression(), debug-location !7
    DBG_VALUE %0, $noreg, !5, !DIExpression(), debug-location !7
    DBG_VALUE %0, $noreg, !5, !DIExpression(), debug-location !7
    DBG_VALUE %0, $noreg, !5, !DIExpression(), debug-location !7
    DBG_VALUE %0, $noreg, !5, !DIExpression(), debug-location !7
    DBG_VALUE %0, $noreg, !5, !DIExpression(), debug-location !7
    DBG_VALUE %0, $noreg, !5, !DIExpression(), debug-location !7
    DBG_VALUE %0, $noreg, !5, !DIExpression(), debug-location !7
    %3:sreg_32 = S_CSELECT_B32 killed %2, killed %1, implicit $scc
    %4:sreg_32 = S_ADD_I32 %0, killed %3, implicit-def dead $scc
    S_ENDPGM 0, implicit %4
...