test/CodeGen/AMDGPU/no-limit-coalesce.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgcn -run-pass register-coalescer -o - %s | FileCheck %s

# Check that coalescer may create wider register tuple than in source.
---
name:            no_limit_coalesce
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr16, $sgpr17

    ; CHECK-LABEL: name: no_limit_coalesce
    ; CHECK: liveins: $sgpr16, $sgpr17
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub1:sgpr_64 = COPY $sgpr17
    ; CHECK-NEXT: [[COPY:%[0-9]+]].sub0:sgpr_64 = COPY $sgpr16
    ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    ; CHECK-NEXT: INLINEASM &"; def $0", attdialect, regdef:VReg_64, def undef %5.sub0_sub1
    ; CHECK-NEXT: GLOBAL_STORE_DWORDX4_SADDR [[V_MOV_B32_e32_]], %5.sub1_sub2_sub3_sub4, [[COPY]], 0, 0, implicit $exec :: (store (s128), addrspace 1)
    ; CHECK-NEXT: SI_RETURN
    %0:sgpr_32 = COPY killed $sgpr17
    %1:sgpr_32 = COPY killed $sgpr16
    undef %2.sub0:sgpr_64 = COPY killed %1
    %2.sub1:sgpr_64 = COPY killed %0
    %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    INLINEASM &"; def $0", attdialect, regdef:VReg_64, def %4:vreg_64
    undef %5.sub0:vreg_128 = COPY killed %4.sub1
    GLOBAL_STORE_DWORDX4_SADDR killed %3, killed %5, killed %2, 0, 0, implicit $exec :: (store (s128), addrspace 1)
    SI_RETURN
...

---
name:            allow_coalesce
tracksRegLiveness: true
registers:
  - { id: 0, class: sreg_32_xm0, preferred-register: '%0' }
  - { id: 1, class: vreg_64, preferred-register: '%1' }
body:             |
  bb.0:
    liveins: $sgpr0, $vgpr0_vgpr1

    ; CHECK-LABEL: name: allow_coalesce
    ; CHECK: liveins: $sgpr0, $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub1:vreg_128 = COPY $sgpr0
    ; CHECK-NEXT: FLAT_STORE_DWORDX2 $vgpr0_vgpr1, [[COPY]].sub0_sub1, 0, 0, implicit $exec, implicit $flat_scr
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_96 = IMPLICIT_DEF
    ; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0_sub1:vreg_96 = COPY [[DEF]]
    ; CHECK-NEXT: FLAT_STORE_DWORDX3 $vgpr0_vgpr1, [[COPY1]], 0, 0, implicit $exec, implicit $flat_scr
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_128 = IMPLICIT_DEF
    ; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0_sub1_sub2:vreg_128 = COPY [[DEF1]]
    ; CHECK-NEXT: FLAT_STORE_DWORDX4 $vgpr0_vgpr1, [[COPY2]], 0, 0, implicit $exec, implicit $flat_scr
    %2:vreg_64 = IMPLICIT_DEF
    undef %3.sub0:vreg_64 = COPY $sgpr0
    %3.sub1:vreg_64 = COPY %2.sub0
    undef %4.sub0:vreg_64 = COPY %3.sub1
    %4.sub1:vreg_64 = COPY %3.sub0
    FLAT_STORE_DWORDX2 $vgpr0_vgpr1, killed %4, 0, 0, implicit $exec, implicit $flat_scr

    %5:vreg_96 = IMPLICIT_DEF
    undef %6.sub0_sub1:vreg_96 = COPY %5
    %6.sub2:vreg_96 = COPY %2.sub0
    FLAT_STORE_DWORDX3 $vgpr0_vgpr1, killed %6, 0, 0, implicit $exec, implicit $flat_scr

    %7:vreg_128 = IMPLICIT_DEF
    undef %8.sub0_sub1_sub2:vreg_128 = COPY %7
    %8.sub3:vreg_128 = COPY %2.sub0
    FLAT_STORE_DWORDX4 $vgpr0_vgpr1, killed %8, 0, 0, implicit $exec, implicit $flat_scr

...