test/CodeGen/AMDGPU/itofp-odd-width-load.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -check-prefix=GFX900 %s
; RUN: llc -mtriple=amdgpu12.50-amd-amdhsa < %s | FileCheck -check-prefix=GFX1250 %s

; A uniform constant or invariant load of 24 or 48 bits aligned to 4 bytes is
; widened and keeps its extension. Other loads are split and extend in the
; high part load.

define amdgpu_kernel void @sitofp_i24_constant_align4(ptr addrspace(4) %in, ptr addrspace(1) %out) {
; GFX900-LABEL: sitofp_i24_constant_align4:
; GFX900:       ; %bb.0:
; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX900-NEXT:    v_mov_b32_e32 v1, 0
; GFX900-NEXT:    s_waitcnt lgkmcnt(0)
; GFX900-NEXT:    s_load_dword s0, s[0:1], 0x0
; GFX900-NEXT:    s_waitcnt lgkmcnt(0)
; GFX900-NEXT:    s_bfe_i32 s0, s0, 0x180000
; GFX900-NEXT:    v_cvt_f32_i32_e32 v0, s0
; GFX900-NEXT:    global_store_dword v1, v0, s[2:3]
; GFX900-NEXT:    s_endpgm
;
; GFX1250-LABEL: sitofp_i24_constant_align4:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0 nv
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    s_load_b32 s0, s[0:1], 0x0 nv
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    s_bfe_i32 s0, s0, 0x180000
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3)
; GFX1250-NEXT:    s_cvt_f32_i32 s0, s0
; GFX1250-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
; GFX1250-NEXT:    global_store_b32 v0, v1, s[2:3]
; GFX1250-NEXT:    s_endpgm
  %v = load i24, ptr addrspace(4) %in, align 4
  %c = sitofp i24 %v to float
  store float %c, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @sitofp_i24_constant_align2(ptr addrspace(4) %in, ptr addrspace(1) %out) {
; GFX900-LABEL: sitofp_i24_constant_align2:
; GFX900:       ; %bb.0:
; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX900-NEXT:    v_mov_b32_e32 v0, 0
; GFX900-NEXT:    s_waitcnt lgkmcnt(0)
; GFX900-NEXT:    global_load_sbyte v1, v0, s[0:1] offset:2
; GFX900-NEXT:    global_load_ushort v2, v0, s[0:1]
; GFX900-NEXT:    s_waitcnt vmcnt(1)
; GFX900-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX900-NEXT:    s_waitcnt vmcnt(0)
; GFX900-NEXT:    v_or_b32_e32 v1, v2, v1
; GFX900-NEXT:    v_cvt_f32_i32_e32 v1, v1
; GFX900-NEXT:    global_store_dword v0, v1, s[2:3]
; GFX900-NEXT:    s_endpgm
;
; GFX1250-LABEL: sitofp_i24_constant_align2:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0 nv
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    s_clause 0x1
; GFX1250-NEXT:    s_load_i8 s4, s[0:1], 0x2 nv
; GFX1250-NEXT:    s_load_u16 s5, s[0:1], 0x0 nv
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    s_lshl_b32 s0, s4, 16
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-NEXT:    s_or_b32 s0, s5, s0
; GFX1250-NEXT:    s_cvt_f32_i32 s0, s0
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
; GFX1250-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
; GFX1250-NEXT:    global_store_b32 v0, v1, s[2:3]
; GFX1250-NEXT:    s_endpgm
  %v = load i24, ptr addrspace(4) %in, align 2
  %c = sitofp i24 %v to float
  store float %c, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @sitofp_i24_global_invariant_align4(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; GFX900-LABEL: sitofp_i24_global_invariant_align4:
; GFX900:       ; %bb.0:
; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX900-NEXT:    v_mov_b32_e32 v1, 0
; GFX900-NEXT:    s_waitcnt lgkmcnt(0)
; GFX900-NEXT:    s_load_dword s0, s[0:1], 0x0
; GFX900-NEXT:    s_waitcnt lgkmcnt(0)
; GFX900-NEXT:    s_bfe_i32 s0, s0, 0x180000
; GFX900-NEXT:    v_cvt_f32_i32_e32 v0, s0
; GFX900-NEXT:    global_store_dword v1, v0, s[2:3]
; GFX900-NEXT:    s_endpgm
;
; GFX1250-LABEL: sitofp_i24_global_invariant_align4:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0 nv
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    s_load_b32 s0, s[0:1], 0x0 nv
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    s_bfe_i32 s0, s0, 0x180000
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3)
; GFX1250-NEXT:    s_cvt_f32_i32 s0, s0
; GFX1250-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
; GFX1250-NEXT:    global_store_b32 v0, v1, s[2:3]
; GFX1250-NEXT:    s_endpgm
  %v = load i24, ptr addrspace(1) %in, align 4, !invariant.load !0
  %c = sitofp i24 %v to float
  store float %c, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @sitofp_i24_global_align4(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; GFX900-LABEL: sitofp_i24_global_align4:
; GFX900:       ; %bb.0:
; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX900-NEXT:    v_mov_b32_e32 v0, 0
; GFX900-NEXT:    s_waitcnt lgkmcnt(0)
; GFX900-NEXT:    global_load_sbyte v1, v0, s[0:1] offset:2
; GFX900-NEXT:    global_load_ushort v2, v0, s[0:1]
; GFX900-NEXT:    s_waitcnt vmcnt(1)
; GFX900-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX900-NEXT:    s_waitcnt vmcnt(0)
; GFX900-NEXT:    v_or_b32_e32 v1, v2, v1
; GFX900-NEXT:    v_cvt_f32_i32_e32 v1, v1
; GFX900-NEXT:    global_store_dword v0, v1, s[2:3]
; GFX900-NEXT:    s_endpgm
;
; GFX1250-LABEL: sitofp_i24_global_align4:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0 nv
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    s_clause 0x1
; GFX1250-NEXT:    s_load_i8 s4, s[0:1], 0x2
; GFX1250-NEXT:    s_load_u16 s5, s[0:1], 0x0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    s_lshl_b32 s0, s4, 16
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-NEXT:    s_or_b32 s0, s5, s0
; GFX1250-NEXT:    s_cvt_f32_i32 s0, s0
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
; GFX1250-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
; GFX1250-NEXT:    global_store_b32 v0, v1, s[2:3]
; GFX1250-NEXT:    s_endpgm
  %v = load i24, ptr addrspace(1) %in, align 4
  %c = sitofp i24 %v to float
  store float %c, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @sitofp_i48_constant_align8(ptr addrspace(4) %in, ptr addrspace(1) %out) {
; GFX900-LABEL: sitofp_i48_constant_align8:
; GFX900:       ; %bb.0:
; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX900-NEXT:    v_mov_b32_e32 v1, 0
; GFX900-NEXT:    s_waitcnt lgkmcnt(0)
; GFX900-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX900-NEXT:    s_waitcnt lgkmcnt(0)
; GFX900-NEXT:    s_mov_b32 s4, s1
; GFX900-NEXT:    s_bfe_i64 s[4:5], s[4:5], 0x100000
; GFX900-NEXT:    s_xor_b32 s5, s0, s4
; GFX900-NEXT:    s_mov_b32 s1, s4
; GFX900-NEXT:    s_flbit_i32 s4, s4
; GFX900-NEXT:    s_ashr_i32 s5, s5, 31
; GFX900-NEXT:    s_add_i32 s5, s5, 32
; GFX900-NEXT:    s_add_i32 s4, s4, -1
; GFX900-NEXT:    s_min_u32 s4, s4, s5
; GFX900-NEXT:    s_lshl_b64 s[0:1], s[0:1], s4
; GFX900-NEXT:    s_min_u32 s0, s0, 1
; GFX900-NEXT:    s_or_b32 s0, s1, s0
; GFX900-NEXT:    v_cvt_f32_i32_e32 v0, s0
; GFX900-NEXT:    s_sub_i32 s0, 32, s4
; GFX900-NEXT:    v_ldexp_f32 v0, v0, s0
; GFX900-NEXT:    global_store_dword v1, v0, s[2:3]
; GFX900-NEXT:    s_endpgm
;
; GFX1250-LABEL: sitofp_i48_constant_align8:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0 nv
; GFX1250-NEXT:    v_mov_b32_e32 v0, 0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0 nv
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    s_mov_b32 s4, s1
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-NEXT:    s_bfe_i64 s[4:5], s[4:5], 0x100000
; GFX1250-NEXT:    s_xor_b32 s1, s0, s4
; GFX1250-NEXT:    s_cls_i32 s5, s4
; GFX1250-NEXT:    s_ashr_i32 s1, s1, 31
; GFX1250-NEXT:    s_add_co_i32 s5, s5, -1
; GFX1250-NEXT:    s_add_co_i32 s6, s1, 32
; GFX1250-NEXT:    s_mov_b32 s1, s4
; GFX1250-NEXT:    s_min_u32 s4, s5, s6
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-NEXT:    s_lshl_b64 s[0:1], s[0:1], s4
; GFX1250-NEXT:    s_min_u32 s0, s0, 1
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_3)
; GFX1250-NEXT:    s_or_b32 s0, s1, s0
; GFX1250-NEXT:    s_sub_co_i32 s1, 32, s4
; GFX1250-NEXT:    s_cvt_f32_i32 s0, s0
; GFX1250-NEXT:    v_ldexp_f32 v1, s0, s1
; GFX1250-NEXT:    global_store_b32 v0, v1, s[2:3]
; GFX1250-NEXT:    s_endpgm
  %v = load i48, ptr addrspace(4) %in, align 8
  %c = sitofp i48 %v to float
  store float %c, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @uitofp_i48_constant_align8(ptr addrspace(4) %in, ptr addrspace(1) %out) {
; GFX900-LABEL: uitofp_i48_constant_align8:
; GFX900:       ; %bb.0:
; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX900-NEXT:    v_mov_b32_e32 v1, 0
; GFX900-NEXT:    s_waitcnt lgkmcnt(0)
; GFX900-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX900-NEXT:    s_waitcnt lgkmcnt(0)
; GFX900-NEXT:    s_and_b32 s1, s1, 0xffff
; GFX900-NEXT:    s_flbit_i32_b32 s4, s1
; GFX900-NEXT:    s_min_u32 s4, s4, 32
; GFX900-NEXT:    s_lshl_b64 s[0:1], s[0:1], s4
; GFX900-NEXT:    s_min_u32 s0, s0, 1
; GFX900-NEXT:    s_or_b32 s0, s1, s0
; GFX900-NEXT:    v_cvt_f32_u32_e32 v0, s0
; GFX900-NEXT:    s_sub_i32 s0, 32, s4
; GFX900-NEXT:    v_ldexp_f32 v0, v0, s0
; GFX900-NEXT:    global_store_dword v1, v0, s[2:3]
; GFX900-NEXT:    s_endpgm
;
; GFX1250-LABEL: uitofp_i48_constant_align8:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0 nv
; GFX1250-NEXT:    v_mov_b32_e32 v0, 0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0 nv
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    s_and_b32 s1, s1, 0xffff
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-NEXT:    s_clz_i32_u32 s4, s1
; GFX1250-NEXT:    s_min_u32 s4, s4, 32
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-NEXT:    s_lshl_b64 s[0:1], s[0:1], s4
; GFX1250-NEXT:    s_min_u32 s0, s0, 1
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_3)
; GFX1250-NEXT:    s_or_b32 s0, s1, s0
; GFX1250-NEXT:    s_sub_co_i32 s1, 32, s4
; GFX1250-NEXT:    s_cvt_f32_u32 s0, s0
; GFX1250-NEXT:    v_ldexp_f32 v1, s0, s1
; GFX1250-NEXT:    global_store_b32 v0, v1, s[2:3]
; GFX1250-NEXT:    s_endpgm
  %v = load i48, ptr addrspace(4) %in, align 8
  %c = uitofp i48 %v to float
  store float %c, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @sitofp_i48_constant_align2(ptr addrspace(4) %in, ptr addrspace(1) %out) {
; GFX900-LABEL: sitofp_i48_constant_align2:
; GFX900:       ; %bb.0:
; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX900-NEXT:    v_mov_b32_e32 v2, 0
; GFX900-NEXT:    s_waitcnt lgkmcnt(0)
; GFX900-NEXT:    global_load_sshort v1, v2, s[0:1] offset:4
; GFX900-NEXT:    global_load_dword v0, v2, s[0:1]
; GFX900-NEXT:    s_waitcnt vmcnt(1)
; GFX900-NEXT:    v_ffbh_i32_e32 v4, v1
; GFX900-NEXT:    s_waitcnt vmcnt(0)
; GFX900-NEXT:    v_xor_b32_e32 v3, v0, v1
; GFX900-NEXT:    v_ashrrev_i32_e32 v3, 31, v3
; GFX900-NEXT:    v_add_u32_e32 v3, 32, v3
; GFX900-NEXT:    v_add_u32_e32 v4, -1, v4
; GFX900-NEXT:    v_min_u32_e32 v3, v4, v3
; GFX900-NEXT:    v_lshlrev_b64 v[0:1], v3, v[0:1]
; GFX900-NEXT:    v_min_u32_e32 v0, 1, v0
; GFX900-NEXT:    v_or_b32_e32 v0, v1, v0
; GFX900-NEXT:    v_cvt_f32_i32_e32 v0, v0
; GFX900-NEXT:    v_sub_u32_e32 v1, 32, v3
; GFX900-NEXT:    v_ldexp_f32 v0, v0, v1
; GFX900-NEXT:    global_store_dword v2, v0, s[2:3]
; GFX900-NEXT:    s_endpgm
;
; GFX1250-LABEL: sitofp_i48_constant_align2:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0 nv
; GFX1250-NEXT:    v_mov_b32_e32 v2, 0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    global_load_b32 v0, v2, s[0:1] nv
; GFX1250-NEXT:    s_wait_xcnt 0x0
; GFX1250-NEXT:    s_load_u16 s0, s[0:1], 0x4 nv
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    s_bfe_i64 s[0:1], s[0:1], 0x100000
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT:    v_mov_b32_e32 v1, s0
; GFX1250-NEXT:    s_wait_loadcnt 0x0
; GFX1250-NEXT:    v_readfirstlane_b32 s4, v0
; GFX1250-NEXT:    s_xor_b32 s1, s4, s0
; GFX1250-NEXT:    s_cls_i32 s0, s0
; GFX1250-NEXT:    s_ashr_i32 s1, s1, 31
; GFX1250-NEXT:    s_add_co_i32 s0, s0, -1
; GFX1250-NEXT:    s_add_co_i32 s1, s1, 32
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-NEXT:    s_min_u32 s0, s0, s1
; GFX1250-NEXT:    v_lshlrev_b64_e32 v[0:1], s0, v[0:1]
; GFX1250-NEXT:    s_sub_co_i32 s0, 32, s0
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT:    v_min_u32_e32 v0, 1, v0
; GFX1250-NEXT:    v_or_b32_e32 v0, v1, v0
; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-NEXT:    v_cvt_f32_i32_e32 v0, v0
; GFX1250-NEXT:    v_ldexp_f32 v0, v0, s0
; GFX1250-NEXT:    global_store_b32 v2, v0, s[2:3]
; GFX1250-NEXT:    s_endpgm
  %v = load i48, ptr addrspace(4) %in, align 2
  %c = sitofp i48 %v to float
  store float %c, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @sitofp_i48_global_invariant_align8(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; GFX900-LABEL: sitofp_i48_global_invariant_align8:
; GFX900:       ; %bb.0:
; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX900-NEXT:    v_mov_b32_e32 v1, 0
; GFX900-NEXT:    s_waitcnt lgkmcnt(0)
; GFX900-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX900-NEXT:    s_waitcnt lgkmcnt(0)
; GFX900-NEXT:    s_mov_b32 s4, s1
; GFX900-NEXT:    s_bfe_i64 s[4:5], s[4:5], 0x100000
; GFX900-NEXT:    s_xor_b32 s5, s0, s4
; GFX900-NEXT:    s_mov_b32 s1, s4
; GFX900-NEXT:    s_flbit_i32 s4, s4
; GFX900-NEXT:    s_ashr_i32 s5, s5, 31
; GFX900-NEXT:    s_add_i32 s5, s5, 32
; GFX900-NEXT:    s_add_i32 s4, s4, -1
; GFX900-NEXT:    s_min_u32 s4, s4, s5
; GFX900-NEXT:    s_lshl_b64 s[0:1], s[0:1], s4
; GFX900-NEXT:    s_min_u32 s0, s0, 1
; GFX900-NEXT:    s_or_b32 s0, s1, s0
; GFX900-NEXT:    v_cvt_f32_i32_e32 v0, s0
; GFX900-NEXT:    s_sub_i32 s0, 32, s4
; GFX900-NEXT:    v_ldexp_f32 v0, v0, s0
; GFX900-NEXT:    global_store_dword v1, v0, s[2:3]
; GFX900-NEXT:    s_endpgm
;
; GFX1250-LABEL: sitofp_i48_global_invariant_align8:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0 nv
; GFX1250-NEXT:    v_mov_b32_e32 v0, 0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    s_load_b64 s[0:1], s[0:1], 0x0 nv
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    s_mov_b32 s4, s1
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-NEXT:    s_bfe_i64 s[4:5], s[4:5], 0x100000
; GFX1250-NEXT:    s_xor_b32 s1, s0, s4
; GFX1250-NEXT:    s_cls_i32 s5, s4
; GFX1250-NEXT:    s_ashr_i32 s1, s1, 31
; GFX1250-NEXT:    s_add_co_i32 s5, s5, -1
; GFX1250-NEXT:    s_add_co_i32 s6, s1, 32
; GFX1250-NEXT:    s_mov_b32 s1, s4
; GFX1250-NEXT:    s_min_u32 s4, s5, s6
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-NEXT:    s_lshl_b64 s[0:1], s[0:1], s4
; GFX1250-NEXT:    s_min_u32 s0, s0, 1
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_3)
; GFX1250-NEXT:    s_or_b32 s0, s1, s0
; GFX1250-NEXT:    s_sub_co_i32 s1, 32, s4
; GFX1250-NEXT:    s_cvt_f32_i32 s0, s0
; GFX1250-NEXT:    v_ldexp_f32 v1, s0, s1
; GFX1250-NEXT:    global_store_b32 v0, v1, s[2:3]
; GFX1250-NEXT:    s_endpgm
  %v = load i48, ptr addrspace(1) %in, align 8, !invariant.load !0
  %c = sitofp i48 %v to float
  store float %c, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @sitofp_i48_global_align8(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; GFX900-LABEL: sitofp_i48_global_align8:
; GFX900:       ; %bb.0:
; GFX900-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX900-NEXT:    v_mov_b32_e32 v2, 0
; GFX900-NEXT:    s_waitcnt lgkmcnt(0)
; GFX900-NEXT:    global_load_sshort v1, v2, s[0:1] offset:4
; GFX900-NEXT:    s_load_dword s0, s[0:1], 0x0
; GFX900-NEXT:    s_waitcnt lgkmcnt(0)
; GFX900-NEXT:    v_mov_b32_e32 v0, s0
; GFX900-NEXT:    s_waitcnt vmcnt(0)
; GFX900-NEXT:    v_xor_b32_e32 v3, s0, v1
; GFX900-NEXT:    v_ffbh_i32_e32 v4, v1
; GFX900-NEXT:    v_ashrrev_i32_e32 v3, 31, v3
; GFX900-NEXT:    v_add_u32_e32 v3, 32, v3
; GFX900-NEXT:    v_add_u32_e32 v4, -1, v4
; GFX900-NEXT:    v_min_u32_e32 v3, v4, v3
; GFX900-NEXT:    v_lshlrev_b64 v[0:1], v3, v[0:1]
; GFX900-NEXT:    v_min_u32_e32 v0, 1, v0
; GFX900-NEXT:    v_or_b32_e32 v0, v1, v0
; GFX900-NEXT:    v_cvt_f32_i32_e32 v0, v0
; GFX900-NEXT:    v_sub_u32_e32 v1, 32, v3
; GFX900-NEXT:    v_ldexp_f32 v0, v0, v1
; GFX900-NEXT:    global_store_dword v2, v0, s[2:3]
; GFX900-NEXT:    s_endpgm
;
; GFX1250-LABEL: sitofp_i48_global_align8:
; GFX1250:       ; %bb.0:
; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT:    s_mov_b64 s[64:65], 0
; GFX1250-NEXT:    v_nop
; GFX1250-NEXT:    global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0 nv
; GFX1250-NEXT:    v_mov_b32_e32 v0, 0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    s_clause 0x1
; GFX1250-NEXT:    s_load_u16 s4, s[0:1], 0x4
; GFX1250-NEXT:    s_load_b32 s6, s[0:1], 0x0
; GFX1250-NEXT:    s_wait_kmcnt 0x0
; GFX1250-NEXT:    s_bfe_i64 s[0:1], s[4:5], 0x100000
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT:    s_xor_b32 s1, s6, s0
; GFX1250-NEXT:    s_cls_i32 s4, s0
; GFX1250-NEXT:    s_ashr_i32 s1, s1, 31
; GFX1250-NEXT:    s_add_co_i32 s4, s4, -1
; GFX1250-NEXT:    s_add_co_i32 s1, s1, 32
; GFX1250-NEXT:    s_mov_b32 s7, s0
; GFX1250-NEXT:    s_min_u32 s4, s4, s1
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-NEXT:    s_lshl_b64 s[0:1], s[6:7], s4
; GFX1250-NEXT:    s_min_u32 s0, s0, 1
; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_3)
; GFX1250-NEXT:    s_or_b32 s0, s1, s0
; GFX1250-NEXT:    s_sub_co_i32 s1, 32, s4
; GFX1250-NEXT:    s_cvt_f32_i32 s0, s0
; GFX1250-NEXT:    v_ldexp_f32 v1, s0, s1
; GFX1250-NEXT:    global_store_b32 v0, v1, s[2:3]
; GFX1250-NEXT:    s_endpgm
  %v = load i48, ptr addrspace(1) %in, align 8
  %c = sitofp i48 %v to float
  store float %c, ptr addrspace(1) %out
  ret void
}

!0 = !{}