test/CodeGen/AMDGPU/fptosi-sat-scalar.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -global-isel=0 -mtriple=amdgcn -mcpu=gfx700 | FileCheck %s --check-prefixes=GFX7,GFX7-ISEL
; RUN: llc < %s -global-isel=1 -mtriple=amdgcn -mcpu=gfx700 | FileCheck %s --check-prefixes=GFX7,GFX7-GI
; RUN: llc < %s -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 | FileCheck %s --check-prefixes=GFX9
; RUN: llc < %s -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 | FileCheck %s --check-prefixes=GFX11,GFX11-FAKE16
; RUN: llc < %s -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 | FileCheck %s --check-prefixes=GFX11,GFX11-TRUE16
; RUN: llc < %s -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 | FileCheck %s --check-prefixes=GFX12,GFX12-ISEL,GFX12-FAKE16
; RUN: llc < %s -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 | FileCheck %s --check-prefixes=GFX12,GFX12-ISEL,GFX12-TRUE16
; RUN: llc < %s -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 | FileCheck %s --check-prefixes=GFX12,GFX12-GI

;
; 32-bit float to signed integer
;

declare   i1 @llvm.fptosi.sat.i1.f32  (float)
declare   i8 @llvm.fptosi.sat.i8.f32  (float)
declare  i16 @llvm.fptosi.sat.i16.f32 (float)
declare  i32 @llvm.fptosi.sat.i32.f32 (float)
declare  i64 @llvm.fptosi.sat.i64.f32 (float)

define i1 @test_signed_i1_f32(float %f) nounwind {
; GFX7-LABEL: test_signed_i1_f32:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_signed_i1_f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX9-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_signed_i1_f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX11-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_signed_i1_f32:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX12-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX12-NEXT:    s_setpc_b64 s[30:31]
    %x = call i1 @llvm.fptosi.sat.i1.f32(float %f)
    ret i1 %x
}

define i8 @test_signed_i8_f32(float %f) nounwind {
; GFX7-ISEL-LABEL: test_signed_i8_f32:
; GFX7-ISEL:       ; %bb.0:
; GFX7-ISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-ISEL-NEXT:    s_movk_i32 s4, 0xff80
; GFX7-ISEL-NEXT:    v_mov_b32_e32 v1, 0x7f
; GFX7-ISEL-NEXT:    v_med3_i32 v0, v0, s4, v1
; GFX7-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_signed_i8_f32:
; GFX7-GI:       ; %bb.0:
; GFX7-GI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-GI-NEXT:    v_mov_b32_e32 v1, 0x7f
; GFX7-GI-NEXT:    v_mov_b32_e32 v2, 0xffffff80
; GFX7-GI-NEXT:    v_med3_i32 v0, v0, v2, v1
; GFX7-GI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_signed_i8_f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX9-NEXT:    s_movk_i32 s4, 0xff80
; GFX9-NEXT:    v_mov_b32_e32 v1, 0x7f
; GFX9-NEXT:    v_med3_i32 v0, v0, s4, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_signed_i8_f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX11-NEXT:    s_movk_i32 s0, 0xff80
; GFX11-NEXT:    v_med3_i32 v0, v0, s0, 0x7f
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_signed_i8_f32:
; GFX12-ISEL:       ; %bb.0:
; GFX12-ISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-ISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-ISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-ISEL-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX12-ISEL-NEXT:    s_movk_i32 s0, 0xff80
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    v_med3_i32 v0, v0, s0, 0x7f
; GFX12-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_signed_i8_f32:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX12-GI-NEXT:    v_mov_b32_e32 v1, 0xffffff80
; GFX12-GI-NEXT:    v_med3_i32 v0, v0, v1, 0x7f
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i8 @llvm.fptosi.sat.i8.f32(float %f)
    ret i8 %x
}

define i16 @test_signed_i16_f32(float %f) nounwind {
; GFX7-ISEL-LABEL: test_signed_i16_f32:
; GFX7-ISEL:       ; %bb.0:
; GFX7-ISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-ISEL-NEXT:    s_movk_i32 s4, 0x8000
; GFX7-ISEL-NEXT:    v_mov_b32_e32 v1, 0x7fff
; GFX7-ISEL-NEXT:    v_med3_i32 v0, v0, s4, v1
; GFX7-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_signed_i16_f32:
; GFX7-GI:       ; %bb.0:
; GFX7-GI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-GI-NEXT:    v_mov_b32_e32 v1, 0x7fff
; GFX7-GI-NEXT:    v_mov_b32_e32 v2, 0xffff8000
; GFX7-GI-NEXT:    v_med3_i32 v0, v0, v2, v1
; GFX7-GI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_signed_i16_f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX9-NEXT:    s_movk_i32 s4, 0x8000
; GFX9-NEXT:    v_mov_b32_e32 v1, 0x7fff
; GFX9-NEXT:    v_med3_i32 v0, v0, s4, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_signed_i16_f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX11-NEXT:    s_movk_i32 s0, 0x8000
; GFX11-NEXT:    v_med3_i32 v0, v0, s0, 0x7fff
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_signed_i16_f32:
; GFX12-ISEL:       ; %bb.0:
; GFX12-ISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-ISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-ISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-ISEL-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX12-ISEL-NEXT:    s_movk_i32 s0, 0x8000
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    v_med3_i32 v0, v0, s0, 0x7fff
; GFX12-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_signed_i16_f32:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX12-GI-NEXT:    v_mov_b32_e32 v1, 0xffff8000
; GFX12-GI-NEXT:    v_med3_i32 v0, v0, v1, 0x7fff
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i16 @llvm.fptosi.sat.i16.f32(float %f)
    ret i16 %x
}

define i32 @test_signed_i32_f32(float %f) nounwind {
; GFX7-LABEL: test_signed_i32_f32:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_signed_i32_f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_signed_i32_f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_signed_i32_f32:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX12-NEXT:    s_setpc_b64 s[30:31]
    %x = call i32 @llvm.fptosi.sat.i32.f32(float %f)
    ret i32 %x
}

define i64 @test_signed_i64_f32(float %f) nounwind {
; GFX7-ISEL-LABEL: test_signed_i64_f32:
; GFX7-ISEL:       ; %bb.0:
; GFX7-ISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT:    v_trunc_f32_e32 v1, v0
; GFX7-ISEL-NEXT:    s_mov_b32 s4, 0x2f800000
; GFX7-ISEL-NEXT:    v_mul_f32_e64 v2, |v1|, s4
; GFX7-ISEL-NEXT:    v_floor_f32_e32 v2, v2
; GFX7-ISEL-NEXT:    s_mov_b32 s4, 0xcf800000
; GFX7-ISEL-NEXT:    v_cvt_u32_f32_e32 v3, v2
; GFX7-ISEL-NEXT:    v_fma_f32 v2, v2, s4, |v1|
; GFX7-ISEL-NEXT:    v_cvt_u32_f32_e32 v2, v2
; GFX7-ISEL-NEXT:    v_ashrrev_i32_e32 v1, 31, v1
; GFX7-ISEL-NEXT:    v_xor_b32_e32 v3, v3, v1
; GFX7-ISEL-NEXT:    s_mov_b32 s4, 0xdf000000
; GFX7-ISEL-NEXT:    v_xor_b32_e32 v2, v2, v1
; GFX7-ISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v1
; GFX7-ISEL-NEXT:    v_subb_u32_e32 v1, vcc, v3, v1, vcc
; GFX7-ISEL-NEXT:    v_cmp_nle_f32_e32 vcc, s4, v0
; GFX7-ISEL-NEXT:    s_mov_b32 s4, 0x5effffff
; GFX7-ISEL-NEXT:    v_cndmask_b32_e64 v2, v2, 0, vcc
; GFX7-ISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], s4, v0
; GFX7-ISEL-NEXT:    v_cndmask_b32_e64 v2, v2, -1, s[4:5]
; GFX7-ISEL-NEXT:    v_cmp_u_f32_e64 s[6:7], v0, v0
; GFX7-ISEL-NEXT:    v_cndmask_b32_e64 v0, v2, 0, s[6:7]
; GFX7-ISEL-NEXT:    v_bfrev_b32_e32 v2, 1
; GFX7-ISEL-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX7-ISEL-NEXT:    v_bfrev_b32_e32 v2, -2
; GFX7-ISEL-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[4:5]
; GFX7-ISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s[6:7]
; GFX7-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_signed_i64_f32:
; GFX7-GI:       ; %bb.0:
; GFX7-GI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT:    v_trunc_f32_e32 v1, v0
; GFX7-GI-NEXT:    v_mov_b32_e32 v2, 0x2f800000
; GFX7-GI-NEXT:    v_mul_f32_e64 v2, |v1|, v2
; GFX7-GI-NEXT:    v_floor_f32_e32 v2, v2
; GFX7-GI-NEXT:    v_mov_b32_e32 v3, 0xcf800000
; GFX7-GI-NEXT:    v_fma_f32 v1, v2, v3, |v1|
; GFX7-GI-NEXT:    v_cvt_u32_f32_e32 v1, v1
; GFX7-GI-NEXT:    v_cvt_u32_f32_e32 v2, v2
; GFX7-GI-NEXT:    v_ashrrev_i32_e32 v3, 31, v0
; GFX7-GI-NEXT:    v_bfrev_b32_e32 v4, 1
; GFX7-GI-NEXT:    v_xor_b32_e32 v1, v1, v3
; GFX7-GI-NEXT:    v_xor_b32_e32 v2, v2, v3
; GFX7-GI-NEXT:    v_sub_i32_e32 v1, vcc, v1, v3
; GFX7-GI-NEXT:    v_subb_u32_e32 v2, vcc, v2, v3, vcc
; GFX7-GI-NEXT:    v_mov_b32_e32 v3, 0xdf000000
; GFX7-GI-NEXT:    v_cmp_nge_f32_e32 vcc, v0, v3
; GFX7-GI-NEXT:    v_mov_b32_e32 v3, 0x5effffff
; GFX7-GI-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
; GFX7-GI-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX7-GI-NEXT:    v_bfrev_b32_e32 v4, -2
; GFX7-GI-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v3
; GFX7-GI-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc
; GFX7-GI-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX7-GI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v0
; GFX7-GI-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
; GFX7-GI-NEXT:    v_cndmask_b32_e64 v1, v2, 0, vcc
; GFX7-GI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_signed_i64_f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_trunc_f32_e32 v1, v0
; GFX9-NEXT:    s_mov_b32 s4, 0x2f800000
; GFX9-NEXT:    v_mul_f32_e64 v2, |v1|, s4
; GFX9-NEXT:    v_floor_f32_e32 v2, v2
; GFX9-NEXT:    s_mov_b32 s4, 0xcf800000
; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v2
; GFX9-NEXT:    v_fma_f32 v2, v2, s4, |v1|
; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
; GFX9-NEXT:    v_ashrrev_i32_e32 v1, 31, v1
; GFX9-NEXT:    v_xor_b32_e32 v3, v3, v1
; GFX9-NEXT:    s_mov_b32 s4, 0xdf000000
; GFX9-NEXT:    v_xor_b32_e32 v2, v2, v1
; GFX9-NEXT:    v_sub_co_u32_e32 v2, vcc, v2, v1
; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v3, v1, vcc
; GFX9-NEXT:    v_cmp_nle_f32_e32 vcc, s4, v0
; GFX9-NEXT:    s_mov_b32 s4, 0x5effffff
; GFX9-NEXT:    v_cndmask_b32_e64 v2, v2, 0, vcc
; GFX9-NEXT:    v_cmp_lt_f32_e64 s[4:5], s4, v0
; GFX9-NEXT:    v_cndmask_b32_e64 v2, v2, -1, s[4:5]
; GFX9-NEXT:    v_cmp_u_f32_e64 s[6:7], v0, v0
; GFX9-NEXT:    v_cndmask_b32_e64 v0, v2, 0, s[6:7]
; GFX9-NEXT:    v_bfrev_b32_e32 v2, 1
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX9-NEXT:    v_bfrev_b32_e32 v2, -2
; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[4:5]
; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s[6:7]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_signed_i64_f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_trunc_f32_e32 v1, v0
; GFX11-NEXT:    v_mul_f32_e64 v2, 0x2f800000, |v1|
; GFX11-NEXT:    v_floor_f32_e32 v2, v2
; GFX11-NEXT:    v_fma_f32 v3, 0xcf800000, v2, |v1|
; GFX11-NEXT:    v_ashrrev_i32_e32 v1, 31, v1
; GFX11-NEXT:    v_cvt_u32_f32_e32 v2, v2
; GFX11-NEXT:    v_cvt_u32_f32_e32 v3, v3
; GFX11-NEXT:    v_xor_b32_e32 v2, v2, v1
; GFX11-NEXT:    v_xor_b32_e32 v3, v3, v1
; GFX11-NEXT:    v_sub_co_u32 v3, vcc_lo, v3, v1
; GFX11-NEXT:    v_sub_co_ci_u32_e64 v1, null, v2, v1, vcc_lo
; GFX11-NEXT:    v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
; GFX11-NEXT:    v_cndmask_b32_e64 v2, v3, 0, vcc_lo
; GFX11-NEXT:    v_cndmask_b32_e64 v1, v1, 0x80000000, vcc_lo
; GFX11-NEXT:    v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v0
; GFX11-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc_lo
; GFX11-NEXT:    v_cndmask_b32_e64 v1, v1, 0x7fffffff, vcc_lo
; GFX11-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc_lo
; GFX11-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_signed_i64_f32:
; GFX12-ISEL:       ; %bb.0:
; GFX12-ISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-ISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-ISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-ISEL-NEXT:    v_trunc_f32_e32 v1, v0
; GFX12-ISEL-NEXT:    v_mul_f32_e64 v2, 0x2f800000, |v1|
; GFX12-ISEL-NEXT:    v_floor_f32_e32 v2, v2
; GFX12-ISEL-NEXT:    v_fma_f32 v3, 0xcf800000, v2, |v1|
; GFX12-ISEL-NEXT:    v_ashrrev_i32_e32 v1, 31, v1
; GFX12-ISEL-NEXT:    v_cvt_u32_f32_e32 v2, v2
; GFX12-ISEL-NEXT:    v_cvt_u32_f32_e32 v3, v3
; GFX12-ISEL-NEXT:    v_xor_b32_e32 v2, v2, v1
; GFX12-ISEL-NEXT:    v_xor_b32_e32 v3, v3, v1
; GFX12-ISEL-NEXT:    v_sub_co_u32 v3, vcc_lo, v3, v1
; GFX12-ISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-ISEL-NEXT:    v_sub_co_ci_u32_e64 v1, null, v2, v1, vcc_lo
; GFX12-ISEL-NEXT:    v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
; GFX12-ISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-ISEL-NEXT:    v_cndmask_b32_e64 v2, v3, 0, vcc_lo
; GFX12-ISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0x80000000, vcc_lo
; GFX12-ISEL-NEXT:    v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v0
; GFX12-ISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-ISEL-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc_lo
; GFX12-ISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0x7fffffff, vcc_lo
; GFX12-ISEL-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-ISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-ISEL-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc_lo
; GFX12-ISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc_lo
; GFX12-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_signed_i64_f32:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    v_trunc_f32_e32 v1, v0
; GFX12-GI-NEXT:    v_ashrrev_i32_e32 v3, 31, v0
; GFX12-GI-NEXT:    v_mul_f32_e64 v2, 0x2f800000, |v1|
; GFX12-GI-NEXT:    v_floor_f32_e32 v2, v2
; GFX12-GI-NEXT:    v_fma_f32 v1, 0xcf800000, v2, |v1|
; GFX12-GI-NEXT:    v_cvt_u32_f32_e32 v2, v2
; GFX12-GI-NEXT:    v_cvt_u32_f32_e32 v1, v1
; GFX12-GI-NEXT:    v_xor_b32_e32 v2, v2, v3
; GFX12-GI-NEXT:    v_xor_b32_e32 v1, v1, v3
; GFX12-GI-NEXT:    v_sub_co_u32 v1, vcc_lo, v1, v3
; GFX12-GI-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GI-NEXT:    v_sub_co_ci_u32_e64 v2, null, v2, v3, vcc_lo
; GFX12-GI-NEXT:    v_cmp_nle_f32_e32 vcc_lo, 0xdf000000, v0
; GFX12-GI-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GI-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc_lo
; GFX12-GI-NEXT:    v_cndmask_b32_e64 v2, v2, 0x80000000, vcc_lo
; GFX12-GI-NEXT:    v_cmp_lt_f32_e32 vcc_lo, 0x5effffff, v0
; GFX12-GI-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GI-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo
; GFX12-GI-NEXT:    v_cndmask_b32_e64 v2, v2, 0x7fffffff, vcc_lo
; GFX12-GI-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX12-GI-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GI-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc_lo
; GFX12-GI-NEXT:    v_cndmask_b32_e64 v1, v2, 0, vcc_lo
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i64 @llvm.fptosi.sat.i64.f32(float %f)
    ret i64 %x
}

define i1 @test_s_signed_i1_f32(float inreg %f) nounwind {
; GFX7-LABEL: test_s_signed_i1_f32:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_cvt_i32_f32_e32 v0, s16
; GFX7-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_signed_i1_f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i32_f32_e32 v0, s16
; GFX9-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_signed_i1_f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cvt_i32_f32_e32 v0, s0
; GFX11-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_s_signed_i1_f32:
; GFX12-ISEL:       ; %bb.0:
; GFX12-ISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-ISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-ISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-ISEL-NEXT:    s_cvt_i32_f32 s0, s0
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    v_med3_i32 v0, s0, -1, 0
; GFX12-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_signed_i1_f32:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    s_cvt_i32_f32 s0, s0
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_min_i32 s0, s0, 0
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_max_i32 s0, s0, -1
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i1 @llvm.fptosi.sat.i1.f32(float %f)
    ret i1 %x
}

define i8 @test_s_signed_i8_f32(float inreg %f) nounwind {
; GFX7-ISEL-LABEL: test_s_signed_i8_f32:
; GFX7-ISEL:       ; %bb.0:
; GFX7-ISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT:    v_cvt_i32_f32_e32 v0, s16
; GFX7-ISEL-NEXT:    s_movk_i32 s4, 0xff80
; GFX7-ISEL-NEXT:    v_mov_b32_e32 v1, 0x7f
; GFX7-ISEL-NEXT:    v_med3_i32 v0, v0, s4, v1
; GFX7-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_s_signed_i8_f32:
; GFX7-GI:       ; %bb.0:
; GFX7-GI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT:    v_cvt_i32_f32_e32 v0, s16
; GFX7-GI-NEXT:    v_mov_b32_e32 v1, 0x7f
; GFX7-GI-NEXT:    v_mov_b32_e32 v2, 0xffffff80
; GFX7-GI-NEXT:    v_med3_i32 v0, v0, v2, v1
; GFX7-GI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_signed_i8_f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i32_f32_e32 v0, s16
; GFX9-NEXT:    s_movk_i32 s4, 0xff80
; GFX9-NEXT:    v_mov_b32_e32 v1, 0x7f
; GFX9-NEXT:    v_med3_i32 v0, v0, s4, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_signed_i8_f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cvt_i32_f32_e32 v0, s0
; GFX11-NEXT:    s_movk_i32 s0, 0xff80
; GFX11-NEXT:    v_med3_i32 v0, v0, s0, 0x7f
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_s_signed_i8_f32:
; GFX12-ISEL:       ; %bb.0:
; GFX12-ISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-ISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-ISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-ISEL-NEXT:    v_mov_b32_e32 v0, 0x7f
; GFX12-ISEL-NEXT:    s_cvt_i32_f32 s0, s0
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    v_med3_i32 v0, 0xffffff80, s0, v0
; GFX12-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_signed_i8_f32:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    s_cvt_i32_f32 s0, s0
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_min_i32 s0, s0, 0x7f
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_max_i32 s0, s0, 0xffffff80
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i8 @llvm.fptosi.sat.i8.f32(float %f)
    ret i8 %x
}

define i16 @test_s_signed_i16_f32(float inreg %f) nounwind {
; GFX7-ISEL-LABEL: test_s_signed_i16_f32:
; GFX7-ISEL:       ; %bb.0:
; GFX7-ISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT:    v_cvt_i32_f32_e32 v0, s16
; GFX7-ISEL-NEXT:    s_movk_i32 s4, 0x8000
; GFX7-ISEL-NEXT:    v_mov_b32_e32 v1, 0x7fff
; GFX7-ISEL-NEXT:    v_med3_i32 v0, v0, s4, v1
; GFX7-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_s_signed_i16_f32:
; GFX7-GI:       ; %bb.0:
; GFX7-GI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT:    v_cvt_i32_f32_e32 v0, s16
; GFX7-GI-NEXT:    v_mov_b32_e32 v1, 0x7fff
; GFX7-GI-NEXT:    v_mov_b32_e32 v2, 0xffff8000
; GFX7-GI-NEXT:    v_med3_i32 v0, v0, v2, v1
; GFX7-GI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_signed_i16_f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i32_f32_e32 v0, s16
; GFX9-NEXT:    s_movk_i32 s4, 0x8000
; GFX9-NEXT:    v_mov_b32_e32 v1, 0x7fff
; GFX9-NEXT:    v_med3_i32 v0, v0, s4, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_signed_i16_f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cvt_i32_f32_e32 v0, s0
; GFX11-NEXT:    s_movk_i32 s0, 0x8000
; GFX11-NEXT:    v_med3_i32 v0, v0, s0, 0x7fff
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_s_signed_i16_f32:
; GFX12-ISEL:       ; %bb.0:
; GFX12-ISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-ISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-ISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-ISEL-NEXT:    v_mov_b32_e32 v0, 0x7fff
; GFX12-ISEL-NEXT:    s_cvt_i32_f32 s0, s0
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    v_med3_i32 v0, 0xffff8000, s0, v0
; GFX12-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_signed_i16_f32:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    s_cvt_i32_f32 s0, s0
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_min_i32 s0, s0, 0x7fff
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_max_i32 s0, s0, 0xffff8000
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i16 @llvm.fptosi.sat.i16.f32(float %f)
    ret i16 %x
}

define i32 @test_s_signed_i32_f32(float inreg %f) nounwind {
; GFX7-LABEL: test_s_signed_i32_f32:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_cvt_i32_f32_e32 v0, s16
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_signed_i32_f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i32_f32_e32 v0, s16
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_signed_i32_f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cvt_i32_f32_e32 v0, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_s_signed_i32_f32:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    s_cvt_i32_f32 s0, s0
; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-NEXT:    s_setpc_b64 s[30:31]
    %x = call i32 @llvm.fptosi.sat.i32.f32(float %f)
    ret i32 %x
}

define i64 @test_s_signed_i64_f32(float inreg %f) nounwind {
; GFX7-ISEL-LABEL: test_s_signed_i64_f32:
; GFX7-ISEL:       ; %bb.0:
; GFX7-ISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT:    v_trunc_f32_e32 v0, s16
; GFX7-ISEL-NEXT:    s_mov_b32 s4, 0x2f800000
; GFX7-ISEL-NEXT:    v_mul_f32_e64 v1, |v0|, s4
; GFX7-ISEL-NEXT:    v_floor_f32_e32 v1, v1
; GFX7-ISEL-NEXT:    s_mov_b32 s4, 0xcf800000
; GFX7-ISEL-NEXT:    v_fma_f32 v2, v1, s4, |v0|
; GFX7-ISEL-NEXT:    v_cvt_u32_f32_e32 v2, v2
; GFX7-ISEL-NEXT:    v_cvt_u32_f32_e32 v1, v1
; GFX7-ISEL-NEXT:    v_readfirstlane_b32 s6, v0
; GFX7-ISEL-NEXT:    s_ashr_i32 s6, s6, 31
; GFX7-ISEL-NEXT:    v_readfirstlane_b32 s4, v2
; GFX7-ISEL-NEXT:    v_readfirstlane_b32 s5, v1
; GFX7-ISEL-NEXT:    s_mov_b32 s7, s6
; GFX7-ISEL-NEXT:    s_xor_b64 s[4:5], s[4:5], s[6:7]
; GFX7-ISEL-NEXT:    s_sub_u32 s7, s4, s6
; GFX7-ISEL-NEXT:    v_mov_b32_e32 v0, 0xdf000000
; GFX7-ISEL-NEXT:    s_subb_u32 s10, s5, s6
; GFX7-ISEL-NEXT:    v_cmp_nge_f32_e32 vcc, s16, v0
; GFX7-ISEL-NEXT:    s_and_b64 s[4:5], vcc, exec
; GFX7-ISEL-NEXT:    v_mov_b32_e32 v0, 0x5effffff
; GFX7-ISEL-NEXT:    v_cmp_gt_f32_e64 s[4:5], s16, v0
; GFX7-ISEL-NEXT:    s_cselect_b32 s8, 0, s7
; GFX7-ISEL-NEXT:    s_and_b64 s[6:7], s[4:5], exec
; GFX7-ISEL-NEXT:    v_cmp_u_f32_e64 s[6:7], s16, s16
; GFX7-ISEL-NEXT:    s_cselect_b32 s11, -1, s8
; GFX7-ISEL-NEXT:    s_and_b64 s[8:9], s[6:7], exec
; GFX7-ISEL-NEXT:    s_cselect_b32 s11, 0, s11
; GFX7-ISEL-NEXT:    s_and_b64 s[8:9], vcc, exec
; GFX7-ISEL-NEXT:    s_cselect_b32 s8, 0x80000000, s10
; GFX7-ISEL-NEXT:    s_and_b64 s[4:5], s[4:5], exec
; GFX7-ISEL-NEXT:    s_cselect_b32 s8, 0x7fffffff, s8
; GFX7-ISEL-NEXT:    s_and_b64 s[4:5], s[6:7], exec
; GFX7-ISEL-NEXT:    s_cselect_b32 s4, 0, s8
; GFX7-ISEL-NEXT:    v_mov_b32_e32 v0, s11
; GFX7-ISEL-NEXT:    v_mov_b32_e32 v1, s4
; GFX7-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_s_signed_i64_f32:
; GFX7-GI:       ; %bb.0:
; GFX7-GI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT:    v_trunc_f32_e32 v0, s16
; GFX7-GI-NEXT:    v_mov_b32_e32 v1, 0x2f800000
; GFX7-GI-NEXT:    v_mul_f32_e64 v1, |v0|, v1
; GFX7-GI-NEXT:    v_floor_f32_e32 v1, v1
; GFX7-GI-NEXT:    v_mov_b32_e32 v2, 0xcf800000
; GFX7-GI-NEXT:    v_fma_f32 v0, v1, v2, |v0|
; GFX7-GI-NEXT:    v_cvt_u32_f32_e32 v0, v0
; GFX7-GI-NEXT:    v_cvt_u32_f32_e32 v1, v1
; GFX7-GI-NEXT:    s_ashr_i32 s4, s16, 31
; GFX7-GI-NEXT:    v_mov_b32_e32 v2, s4
; GFX7-GI-NEXT:    v_xor_b32_e32 v0, s4, v0
; GFX7-GI-NEXT:    v_xor_b32_e32 v1, s4, v1
; GFX7-GI-NEXT:    v_subrev_i32_e32 v0, vcc, s4, v0
; GFX7-GI-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
; GFX7-GI-NEXT:    v_mov_b32_e32 v2, 0xdf000000
; GFX7-GI-NEXT:    v_bfrev_b32_e32 v3, 1
; GFX7-GI-NEXT:    v_cmp_nge_f32_e32 vcc, s16, v2
; GFX7-GI-NEXT:    v_mov_b32_e32 v2, 0x5effffff
; GFX7-GI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX7-GI-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX7-GI-NEXT:    v_bfrev_b32_e32 v3, -2
; GFX7-GI-NEXT:    v_cmp_gt_f32_e32 vcc, s16, v2
; GFX7-GI-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc
; GFX7-GI-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX7-GI-NEXT:    v_cmp_u_f32_e64 s[4:5], s16, s16
; GFX7-GI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[4:5]
; GFX7-GI-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s[4:5]
; GFX7-GI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_signed_i64_f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_trunc_f32_e32 v0, s16
; GFX9-NEXT:    s_mov_b32 s4, 0x2f800000
; GFX9-NEXT:    v_mul_f32_e64 v1, |v0|, s4
; GFX9-NEXT:    v_floor_f32_e32 v1, v1
; GFX9-NEXT:    s_mov_b32 s4, 0xcf800000
; GFX9-NEXT:    v_fma_f32 v2, v1, s4, |v0|
; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT:    v_readfirstlane_b32 s6, v0
; GFX9-NEXT:    s_ashr_i32 s6, s6, 31
; GFX9-NEXT:    v_readfirstlane_b32 s4, v2
; GFX9-NEXT:    v_readfirstlane_b32 s5, v1
; GFX9-NEXT:    s_mov_b32 s7, s6
; GFX9-NEXT:    s_xor_b64 s[4:5], s[4:5], s[6:7]
; GFX9-NEXT:    s_sub_u32 s7, s4, s6
; GFX9-NEXT:    v_mov_b32_e32 v0, 0xdf000000
; GFX9-NEXT:    s_subb_u32 s10, s5, s6
; GFX9-NEXT:    v_cmp_nge_f32_e32 vcc, s16, v0
; GFX9-NEXT:    s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT:    v_mov_b32_e32 v0, 0x5effffff
; GFX9-NEXT:    v_cmp_gt_f32_e64 s[4:5], s16, v0
; GFX9-NEXT:    s_cselect_b32 s8, 0, s7
; GFX9-NEXT:    s_and_b64 s[6:7], s[4:5], exec
; GFX9-NEXT:    v_cmp_u_f32_e64 s[6:7], s16, s16
; GFX9-NEXT:    s_cselect_b32 s11, -1, s8
; GFX9-NEXT:    s_and_b64 s[8:9], s[6:7], exec
; GFX9-NEXT:    s_cselect_b32 s11, 0, s11
; GFX9-NEXT:    s_and_b64 s[8:9], vcc, exec
; GFX9-NEXT:    s_cselect_b32 s8, 0x80000000, s10
; GFX9-NEXT:    s_and_b64 s[4:5], s[4:5], exec
; GFX9-NEXT:    s_cselect_b32 s8, 0x7fffffff, s8
; GFX9-NEXT:    s_and_b64 s[4:5], s[6:7], exec
; GFX9-NEXT:    s_cselect_b32 s4, 0, s8
; GFX9-NEXT:    v_mov_b32_e32 v0, s11
; GFX9-NEXT:    v_mov_b32_e32 v1, s4
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_signed_i64_f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_trunc_f32_e32 v0, s0
; GFX11-NEXT:    v_cmp_lt_f32_e64 s6, 0x5effffff, s0
; GFX11-NEXT:    v_mul_f32_e64 v1, 0x2f800000, |v0|
; GFX11-NEXT:    v_readfirstlane_b32 s1, v0
; GFX11-NEXT:    v_floor_f32_e32 v1, v1
; GFX11-NEXT:    s_ashr_i32 s4, s1, 31
; GFX11-NEXT:    v_cmp_nle_f32_e64 s1, 0xdf000000, s0
; GFX11-NEXT:    s_mov_b32 s5, s4
; GFX11-NEXT:    v_cmp_u_f32_e64 s0, s0, s0
; GFX11-NEXT:    v_fma_f32 v2, 0xcf800000, v1, |v0|
; GFX11-NEXT:    v_cvt_u32_f32_e32 v1, v1
; GFX11-NEXT:    v_cvt_u32_f32_e32 v2, v2
; GFX11-NEXT:    v_readfirstlane_b32 s3, v1
; GFX11-NEXT:    v_readfirstlane_b32 s2, v2
; GFX11-NEXT:    s_xor_b64 s[2:3], s[2:3], s[4:5]
; GFX11-NEXT:    s_sub_u32 s2, s2, s4
; GFX11-NEXT:    s_subb_u32 s3, s3, s4
; GFX11-NEXT:    s_and_b32 s4, s1, exec_lo
; GFX11-NEXT:    s_cselect_b32 s2, 0, s2
; GFX11-NEXT:    s_and_b32 s4, s6, exec_lo
; GFX11-NEXT:    s_cselect_b32 s2, -1, s2
; GFX11-NEXT:    s_and_b32 s4, s0, exec_lo
; GFX11-NEXT:    s_cselect_b32 s2, 0, s2
; GFX11-NEXT:    s_and_b32 s1, s1, exec_lo
; GFX11-NEXT:    s_cselect_b32 s1, 0x80000000, s3
; GFX11-NEXT:    s_and_b32 s3, s6, exec_lo
; GFX11-NEXT:    s_cselect_b32 s1, 0x7fffffff, s1
; GFX11-NEXT:    s_and_b32 s0, s0, exec_lo
; GFX11-NEXT:    s_cselect_b32 s0, 0, s1
; GFX11-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_s_signed_i64_f32:
; GFX12-ISEL:       ; %bb.0:
; GFX12-ISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-ISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-ISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-ISEL-NEXT:    s_trunc_f32 s1, s0
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    s_and_b32 s3, s1, 0x7fffffff
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    s_mul_f32 s2, s3, 0x2f800000
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    s_floor_f32 s4, s2
; GFX12-ISEL-NEXT:    s_ashr_i32 s2, s1, 31
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    s_fmac_f32 s3, s4, 0xcf800000
; GFX12-ISEL-NEXT:    s_cvt_u32_f32 s5, s4
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    s_cvt_u32_f32 s4, s3
; GFX12-ISEL-NEXT:    s_mov_b32 s3, s2
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    s_xor_b64 s[4:5], s[4:5], s[2:3]
; GFX12-ISEL-NEXT:    s_cmp_nge_f32 s0, 0xdf000000
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    s_sub_nc_u64 s[2:3], s[4:5], s[2:3]
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    s_cselect_b32 s1, 0, s2
; GFX12-ISEL-NEXT:    s_cselect_b32 s2, 0x80000000, s3
; GFX12-ISEL-NEXT:    s_cmp_gt_f32 s0, 0x5effffff
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    s_cselect_b32 s2, 0x7fffffff, s2
; GFX12-ISEL-NEXT:    s_cselect_b32 s1, -1, s1
; GFX12-ISEL-NEXT:    s_cmp_u_f32 s0, s0
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    s_cselect_b32 s0, 0, s1
; GFX12-ISEL-NEXT:    s_cselect_b32 s1, 0, s2
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_signed_i64_f32:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    s_trunc_f32 s1, s0
; GFX12-GI-NEXT:    s_mov_b32 s6, 0
; GFX12-GI-NEXT:    s_brev_b32 s7, 1
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_bitset0_b32 s1, 31
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_mul_f32 s2, s1, 0x2f800000
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_floor_f32 s3, s2
; GFX12-GI-NEXT:    s_ashr_i32 s2, s0, 31
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_fmac_f32 s1, s3, 0xcf800000
; GFX12-GI-NEXT:    s_cvt_u32_f32 s5, s3
; GFX12-GI-NEXT:    s_mov_b32 s3, s2
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_cvt_u32_f32 s4, s1
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_xor_b64 s[4:5], s[4:5], s[2:3]
; GFX12-GI-NEXT:    s_cmp_nge_f32 s0, 0xdf000000
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_sub_nc_u64 s[2:3], s[4:5], s[2:3]
; GFX12-GI-NEXT:    s_mov_b32 s4, -1
; GFX12-GI-NEXT:    s_brev_b32 s5, -2
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_cselect_b64 s[2:3], s[6:7], s[2:3]
; GFX12-GI-NEXT:    s_cmp_gt_f32 s0, 0x5effffff
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_cselect_b64 s[2:3], s[4:5], s[2:3]
; GFX12-GI-NEXT:    s_cmp_u_f32 s0, s0
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_cselect_b64 s[0:1], 0, s[2:3]
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i64 @llvm.fptosi.sat.i64.f32(float %f)
    ret i64 %x
}

;
; 64-bit float to signed integer
;

declare   i1 @llvm.fptosi.sat.i1.f64  (double)
declare   i8 @llvm.fptosi.sat.i8.f64  (double)
declare  i16 @llvm.fptosi.sat.i16.f64 (double)
declare  i32 @llvm.fptosi.sat.i32.f64 (double)
declare  i64 @llvm.fptosi.sat.i64.f64 (double)

define i1 @test_signed_i1_f64(double %f) nounwind {
; GFX7-LABEL: test_signed_i1_f64:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_cvt_i32_f64_e32 v0, v[0:1]
; GFX7-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_signed_i1_f64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i32_f64_e32 v0, v[0:1]
; GFX9-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_signed_i1_f64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cvt_i32_f64_e32 v0, v[0:1]
; GFX11-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_signed_i1_f64:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_cvt_i32_f64_e32 v0, v[0:1]
; GFX12-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX12-NEXT:    s_setpc_b64 s[30:31]
    %x = call i1 @llvm.fptosi.sat.i1.f64(double %f)
    ret i1 %x
}

define i8 @test_signed_i8_f64(double %f) nounwind {
; GFX7-ISEL-LABEL: test_signed_i8_f64:
; GFX7-ISEL:       ; %bb.0:
; GFX7-ISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT:    v_cvt_i32_f64_e32 v0, v[0:1]
; GFX7-ISEL-NEXT:    s_movk_i32 s4, 0xff80
; GFX7-ISEL-NEXT:    v_mov_b32_e32 v1, 0x7f
; GFX7-ISEL-NEXT:    v_med3_i32 v0, v0, s4, v1
; GFX7-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_signed_i8_f64:
; GFX7-GI:       ; %bb.0:
; GFX7-GI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT:    v_cvt_i32_f64_e32 v0, v[0:1]
; GFX7-GI-NEXT:    v_mov_b32_e32 v1, 0x7f
; GFX7-GI-NEXT:    v_mov_b32_e32 v2, 0xffffff80
; GFX7-GI-NEXT:    v_med3_i32 v0, v0, v2, v1
; GFX7-GI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_signed_i8_f64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i32_f64_e32 v0, v[0:1]
; GFX9-NEXT:    s_movk_i32 s4, 0xff80
; GFX9-NEXT:    v_mov_b32_e32 v1, 0x7f
; GFX9-NEXT:    v_med3_i32 v0, v0, s4, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_signed_i8_f64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cvt_i32_f64_e32 v0, v[0:1]
; GFX11-NEXT:    s_movk_i32 s0, 0xff80
; GFX11-NEXT:    v_med3_i32 v0, v0, s0, 0x7f
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_signed_i8_f64:
; GFX12-ISEL:       ; %bb.0:
; GFX12-ISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-ISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-ISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-ISEL-NEXT:    v_cvt_i32_f64_e32 v0, v[0:1]
; GFX12-ISEL-NEXT:    s_movk_i32 s0, 0xff80
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    v_med3_i32 v0, v0, s0, 0x7f
; GFX12-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_signed_i8_f64:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    v_cvt_i32_f64_e32 v0, v[0:1]
; GFX12-GI-NEXT:    v_mov_b32_e32 v1, 0xffffff80
; GFX12-GI-NEXT:    v_med3_i32 v0, v0, v1, 0x7f
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i8 @llvm.fptosi.sat.i8.f64(double %f)
    ret i8 %x
}

define i16 @test_signed_i16_f64(double %f) nounwind {
; GFX7-ISEL-LABEL: test_signed_i16_f64:
; GFX7-ISEL:       ; %bb.0:
; GFX7-ISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT:    v_cvt_i32_f64_e32 v0, v[0:1]
; GFX7-ISEL-NEXT:    s_movk_i32 s4, 0x8000
; GFX7-ISEL-NEXT:    v_mov_b32_e32 v1, 0x7fff
; GFX7-ISEL-NEXT:    v_med3_i32 v0, v0, s4, v1
; GFX7-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_signed_i16_f64:
; GFX7-GI:       ; %bb.0:
; GFX7-GI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT:    v_cvt_i32_f64_e32 v0, v[0:1]
; GFX7-GI-NEXT:    v_mov_b32_e32 v1, 0x7fff
; GFX7-GI-NEXT:    v_mov_b32_e32 v2, 0xffff8000
; GFX7-GI-NEXT:    v_med3_i32 v0, v0, v2, v1
; GFX7-GI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_signed_i16_f64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i32_f64_e32 v0, v[0:1]
; GFX9-NEXT:    s_movk_i32 s4, 0x8000
; GFX9-NEXT:    v_mov_b32_e32 v1, 0x7fff
; GFX9-NEXT:    v_med3_i32 v0, v0, s4, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_signed_i16_f64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cvt_i32_f64_e32 v0, v[0:1]
; GFX11-NEXT:    s_movk_i32 s0, 0x8000
; GFX11-NEXT:    v_med3_i32 v0, v0, s0, 0x7fff
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_signed_i16_f64:
; GFX12-ISEL:       ; %bb.0:
; GFX12-ISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-ISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-ISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-ISEL-NEXT:    v_cvt_i32_f64_e32 v0, v[0:1]
; GFX12-ISEL-NEXT:    s_movk_i32 s0, 0x8000
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    v_med3_i32 v0, v0, s0, 0x7fff
; GFX12-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_signed_i16_f64:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    v_cvt_i32_f64_e32 v0, v[0:1]
; GFX12-GI-NEXT:    v_mov_b32_e32 v1, 0xffff8000
; GFX12-GI-NEXT:    v_med3_i32 v0, v0, v1, 0x7fff
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i16 @llvm.fptosi.sat.i16.f64(double %f)
    ret i16 %x
}

define i32 @test_signed_i32_f64(double %f) nounwind {
; GFX7-LABEL: test_signed_i32_f64:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_cvt_i32_f64_e32 v0, v[0:1]
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_signed_i32_f64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i32_f64_e32 v0, v[0:1]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_signed_i32_f64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cvt_i32_f64_e32 v0, v[0:1]
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_signed_i32_f64:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_cvt_i32_f64_e32 v0, v[0:1]
; GFX12-NEXT:    s_setpc_b64 s[30:31]
    %x = call i32 @llvm.fptosi.sat.i32.f64(double %f)
    ret i32 %x
}

define i64 @test_signed_i64_f64(double %f) nounwind {
; GFX7-ISEL-LABEL: test_signed_i64_f64:
; GFX7-ISEL:       ; %bb.0:
; GFX7-ISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT:    v_trunc_f64_e32 v[2:3], v[0:1]
; GFX7-ISEL-NEXT:    s_movk_i32 s4, 0xffe0
; GFX7-ISEL-NEXT:    s_mov_b32 s8, 0
; GFX7-ISEL-NEXT:    s_mov_b32 s9, 0xc1f00000
; GFX7-ISEL-NEXT:    s_mov_b32 s5, 0xc3e00000
; GFX7-ISEL-NEXT:    s_mov_b32 s6, -1
; GFX7-ISEL-NEXT:    s_mov_b32 s7, 0x43dfffff
; GFX7-ISEL-NEXT:    v_bfrev_b32_e32 v6, 1
; GFX7-ISEL-NEXT:    v_ldexp_f64 v[4:5], v[2:3], s4
; GFX7-ISEL-NEXT:    s_mov_b32 s4, 0
; GFX7-ISEL-NEXT:    v_cmp_nle_f64_e32 vcc, s[4:5], v[0:1]
; GFX7-ISEL-NEXT:    v_cmp_lt_f64_e64 s[4:5], s[6:7], v[0:1]
; GFX7-ISEL-NEXT:    v_cmp_u_f64_e64 s[6:7], v[0:1], v[0:1]
; GFX7-ISEL-NEXT:    v_floor_f64_e32 v[4:5], v[4:5]
; GFX7-ISEL-NEXT:    v_fma_f64 v[2:3], v[4:5], s[8:9], v[2:3]
; GFX7-ISEL-NEXT:    v_cvt_i32_f64_e32 v7, v[4:5]
; GFX7-ISEL-NEXT:    v_bfrev_b32_e32 v4, -2
; GFX7-ISEL-NEXT:    v_cndmask_b32_e32 v5, v7, v6, vcc
; GFX7-ISEL-NEXT:    v_cndmask_b32_e64 v4, v5, v4, s[4:5]
; GFX7-ISEL-NEXT:    v_cndmask_b32_e64 v1, v4, 0, s[6:7]
; GFX7-ISEL-NEXT:    v_cvt_u32_f64_e32 v0, v[2:3]
; GFX7-ISEL-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX7-ISEL-NEXT:    v_cndmask_b32_e64 v0, v0, -1, s[4:5]
; GFX7-ISEL-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[6:7]
; GFX7-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_signed_i64_f64:
; GFX7-GI:       ; %bb.0:
; GFX7-GI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT:    v_trunc_f64_e32 v[2:3], v[0:1]
; GFX7-GI-NEXT:    v_mov_b32_e32 v4, 0
; GFX7-GI-NEXT:    v_mov_b32_e32 v5, 0x3df00000
; GFX7-GI-NEXT:    v_mov_b32_e32 v6, 0
; GFX7-GI-NEXT:    v_mov_b32_e32 v7, 0xc1f00000
; GFX7-GI-NEXT:    v_cmp_u_f64_e64 s[6:7], v[0:1], v[0:1]
; GFX7-GI-NEXT:    v_mul_f64 v[4:5], v[2:3], v[4:5]
; GFX7-GI-NEXT:    v_floor_f64_e32 v[4:5], v[4:5]
; GFX7-GI-NEXT:    v_fma_f64 v[2:3], v[4:5], v[6:7], v[2:3]
; GFX7-GI-NEXT:    v_mov_b32_e32 v6, -1
; GFX7-GI-NEXT:    v_mov_b32_e32 v7, 0x43dfffff
; GFX7-GI-NEXT:    v_cmp_gt_f64_e64 s[4:5], v[0:1], v[6:7]
; GFX7-GI-NEXT:    v_cvt_u32_f64_e32 v8, v[2:3]
; GFX7-GI-NEXT:    v_mov_b32_e32 v2, 0
; GFX7-GI-NEXT:    v_mov_b32_e32 v3, 0xc3e00000
; GFX7-GI-NEXT:    v_cmp_nge_f64_e32 vcc, v[0:1], v[2:3]
; GFX7-GI-NEXT:    v_cvt_i32_f64_e32 v1, v[4:5]
; GFX7-GI-NEXT:    v_bfrev_b32_e32 v3, 1
; GFX7-GI-NEXT:    v_bfrev_b32_e32 v4, -2
; GFX7-GI-NEXT:    v_cndmask_b32_e64 v2, v8, 0, vcc
; GFX7-GI-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX7-GI-NEXT:    v_cndmask_b32_e64 v2, v2, -1, s[4:5]
; GFX7-GI-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[4:5]
; GFX7-GI-NEXT:    v_cndmask_b32_e64 v0, v2, 0, s[6:7]
; GFX7-GI-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s[6:7]
; GFX7-GI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_signed_i64_f64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_trunc_f64_e32 v[2:3], v[0:1]
; GFX9-NEXT:    s_movk_i32 s4, 0xffe0
; GFX9-NEXT:    s_mov_b32 s8, 0
; GFX9-NEXT:    s_mov_b32 s9, 0xc1f00000
; GFX9-NEXT:    s_mov_b32 s5, 0xc3e00000
; GFX9-NEXT:    s_mov_b32 s6, -1
; GFX9-NEXT:    s_mov_b32 s7, 0x43dfffff
; GFX9-NEXT:    v_bfrev_b32_e32 v6, 1
; GFX9-NEXT:    v_ldexp_f64 v[4:5], v[2:3], s4
; GFX9-NEXT:    s_mov_b32 s4, 0
; GFX9-NEXT:    v_cmp_nle_f64_e32 vcc, s[4:5], v[0:1]
; GFX9-NEXT:    v_cmp_lt_f64_e64 s[4:5], s[6:7], v[0:1]
; GFX9-NEXT:    v_cmp_u_f64_e64 s[6:7], v[0:1], v[0:1]
; GFX9-NEXT:    v_floor_f64_e32 v[4:5], v[4:5]
; GFX9-NEXT:    v_fma_f64 v[2:3], v[4:5], s[8:9], v[2:3]
; GFX9-NEXT:    v_cvt_i32_f64_e32 v7, v[4:5]
; GFX9-NEXT:    v_bfrev_b32_e32 v4, -2
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v7, v6, vcc
; GFX9-NEXT:    v_cndmask_b32_e64 v4, v5, v4, s[4:5]
; GFX9-NEXT:    v_cndmask_b32_e64 v1, v4, 0, s[6:7]
; GFX9-NEXT:    v_cvt_u32_f64_e32 v0, v[2:3]
; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, -1, s[4:5]
; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[6:7]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_signed_i64_f64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_trunc_f64_e32 v[2:3], v[0:1]
; GFX11-NEXT:    v_cmp_nle_f64_e32 vcc_lo, 0xc3e00000, v[0:1]
; GFX11-NEXT:    s_mov_b32 s0, -1
; GFX11-NEXT:    s_mov_b32 s1, 0x43dfffff
; GFX11-NEXT:    v_cmp_lt_f64_e64 s0, s[0:1], v[0:1]
; GFX11-NEXT:    v_cmp_u_f64_e64 s1, v[0:1], v[0:1]
; GFX11-NEXT:    v_ldexp_f64 v[4:5], v[2:3], 0xffffffe0
; GFX11-NEXT:    v_floor_f64_e32 v[4:5], v[4:5]
; GFX11-NEXT:    v_fma_f64 v[2:3], 0xc1f00000, v[4:5], v[2:3]
; GFX11-NEXT:    v_cvt_i32_f64_e32 v4, v[4:5]
; GFX11-NEXT:    v_cvt_u32_f64_e32 v2, v[2:3]
; GFX11-NEXT:    v_cndmask_b32_e64 v3, v4, 0x80000000, vcc_lo
; GFX11-NEXT:    v_cndmask_b32_e64 v3, v3, 0x7fffffff, s0
; GFX11-NEXT:    v_cndmask_b32_e64 v1, v3, 0, s1
; GFX11-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc_lo
; GFX11-NEXT:    v_cndmask_b32_e64 v0, v0, -1, s0
; GFX11-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s1
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_signed_i64_f64:
; GFX12-ISEL:       ; %bb.0:
; GFX12-ISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-ISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-ISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-ISEL-NEXT:    v_trunc_f64_e32 v[2:3], v[0:1]
; GFX12-ISEL-NEXT:    v_cmp_nle_f64_e32 vcc_lo, 0xc3e00000, v[0:1]
; GFX12-ISEL-NEXT:    s_mov_b32 s0, -1
; GFX12-ISEL-NEXT:    s_mov_b32 s1, 0x43dfffff
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    v_cmp_lt_f64_e64 s0, s[0:1], v[0:1]
; GFX12-ISEL-NEXT:    v_cmp_u_f64_e64 s1, v[0:1], v[0:1]
; GFX12-ISEL-NEXT:    v_ldexp_f64 v[4:5], v[2:3], 0xffffffe0
; GFX12-ISEL-NEXT:    v_floor_f64_e32 v[4:5], v[4:5]
; GFX12-ISEL-NEXT:    v_fma_f64 v[2:3], 0xc1f00000, v[4:5], v[2:3]
; GFX12-ISEL-NEXT:    v_cvt_i32_f64_e32 v4, v[4:5]
; GFX12-ISEL-NEXT:    v_cvt_u32_f64_e32 v2, v[2:3]
; GFX12-ISEL-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-ISEL-NEXT:    v_cndmask_b32_e64 v3, v4, 0x80000000, vcc_lo
; GFX12-ISEL-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX12-ISEL-NEXT:    v_cndmask_b32_e64 v3, v3, 0x7fffffff, s0
; GFX12-ISEL-NEXT:    v_cndmask_b32_e64 v1, v3, 0, s1
; GFX12-ISEL-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc_lo
; GFX12-ISEL-NEXT:    v_cndmask_b32_e64 v0, v0, -1, s0
; GFX12-ISEL-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s1
; GFX12-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_signed_i64_f64:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    v_trunc_f64_e32 v[2:3], v[0:1]
; GFX12-GI-NEXT:    v_cmp_nle_f64_e32 vcc_lo, 0xc3e00000, v[0:1]
; GFX12-GI-NEXT:    v_cmp_u_f64_e64 s1, v[0:1], v[0:1]
; GFX12-GI-NEXT:    v_mul_f64_e32 v[4:5], 0x3df00000, v[2:3]
; GFX12-GI-NEXT:    v_floor_f64_e32 v[4:5], v[4:5]
; GFX12-GI-NEXT:    v_fma_f64 v[2:3], 0xc1f00000, v[4:5], v[2:3]
; GFX12-GI-NEXT:    v_cvt_i32_f64_e32 v4, v[4:5]
; GFX12-GI-NEXT:    v_cvt_u32_f64_e32 v6, v[2:3]
; GFX12-GI-NEXT:    v_dual_mov_b32 v2, -1 :: v_dual_mov_b32 v3, 0x43dfffff
; GFX12-GI-NEXT:    v_cmp_gt_f64_e64 s0, v[0:1], v[2:3]
; GFX12-GI-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GI-NEXT:    v_cndmask_b32_e64 v0, v4, 0x80000000, vcc_lo
; GFX12-GI-NEXT:    v_cndmask_b32_e64 v5, v6, 0, vcc_lo
; GFX12-GI-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX12-GI-NEXT:    v_cndmask_b32_e64 v2, v5, -1, s0
; GFX12-GI-NEXT:    v_cndmask_b32_e64 v1, v0, 0x7fffffff, s0
; GFX12-GI-NEXT:    v_cndmask_b32_e64 v0, v2, 0, s1
; GFX12-GI-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s1
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i64 @llvm.fptosi.sat.i64.f64(double %f)
    ret i64 %x
}

define i1 @test_s_signed_i1_f64(double inreg %f) nounwind {
; GFX7-LABEL: test_s_signed_i1_f64:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_cvt_i32_f64_e32 v0, s[16:17]
; GFX7-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_signed_i1_f64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i32_f64_e32 v0, s[16:17]
; GFX9-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_signed_i1_f64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cvt_i32_f64_e32 v0, s[0:1]
; GFX11-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_s_signed_i1_f64:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_cvt_i32_f64_e32 v0, s[0:1]
; GFX12-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX12-NEXT:    s_setpc_b64 s[30:31]
    %x = call i1 @llvm.fptosi.sat.i1.f64(double %f)
    ret i1 %x
}

define i8 @test_s_signed_i8_f64(double inreg %f) nounwind {
; GFX7-ISEL-LABEL: test_s_signed_i8_f64:
; GFX7-ISEL:       ; %bb.0:
; GFX7-ISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT:    v_cvt_i32_f64_e32 v0, s[16:17]
; GFX7-ISEL-NEXT:    s_movk_i32 s4, 0xff80
; GFX7-ISEL-NEXT:    v_mov_b32_e32 v1, 0x7f
; GFX7-ISEL-NEXT:    v_med3_i32 v0, v0, s4, v1
; GFX7-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_s_signed_i8_f64:
; GFX7-GI:       ; %bb.0:
; GFX7-GI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT:    v_cvt_i32_f64_e32 v0, s[16:17]
; GFX7-GI-NEXT:    v_mov_b32_e32 v1, 0x7f
; GFX7-GI-NEXT:    v_mov_b32_e32 v2, 0xffffff80
; GFX7-GI-NEXT:    v_med3_i32 v0, v0, v2, v1
; GFX7-GI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_signed_i8_f64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i32_f64_e32 v0, s[16:17]
; GFX9-NEXT:    s_movk_i32 s4, 0xff80
; GFX9-NEXT:    v_mov_b32_e32 v1, 0x7f
; GFX9-NEXT:    v_med3_i32 v0, v0, s4, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_signed_i8_f64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cvt_i32_f64_e32 v0, s[0:1]
; GFX11-NEXT:    s_movk_i32 s0, 0xff80
; GFX11-NEXT:    v_med3_i32 v0, v0, s0, 0x7f
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_s_signed_i8_f64:
; GFX12-ISEL:       ; %bb.0:
; GFX12-ISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-ISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-ISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-ISEL-NEXT:    v_cvt_i32_f64_e32 v0, s[0:1]
; GFX12-ISEL-NEXT:    s_movk_i32 s0, 0xff80
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    v_med3_i32 v0, v0, s0, 0x7f
; GFX12-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_signed_i8_f64:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    v_cvt_i32_f64_e32 v0, s[0:1]
; GFX12-GI-NEXT:    v_mov_b32_e32 v1, 0xffffff80
; GFX12-GI-NEXT:    v_med3_i32 v0, v0, v1, 0x7f
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i8 @llvm.fptosi.sat.i8.f64(double %f)
    ret i8 %x
}

define i16 @test_s_signed_i16_f64(double inreg %f) nounwind {
; GFX7-ISEL-LABEL: test_s_signed_i16_f64:
; GFX7-ISEL:       ; %bb.0:
; GFX7-ISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT:    v_cvt_i32_f64_e32 v0, s[16:17]
; GFX7-ISEL-NEXT:    s_movk_i32 s4, 0x8000
; GFX7-ISEL-NEXT:    v_mov_b32_e32 v1, 0x7fff
; GFX7-ISEL-NEXT:    v_med3_i32 v0, v0, s4, v1
; GFX7-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_s_signed_i16_f64:
; GFX7-GI:       ; %bb.0:
; GFX7-GI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT:    v_cvt_i32_f64_e32 v0, s[16:17]
; GFX7-GI-NEXT:    v_mov_b32_e32 v1, 0x7fff
; GFX7-GI-NEXT:    v_mov_b32_e32 v2, 0xffff8000
; GFX7-GI-NEXT:    v_med3_i32 v0, v0, v2, v1
; GFX7-GI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_signed_i16_f64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i32_f64_e32 v0, s[16:17]
; GFX9-NEXT:    s_movk_i32 s4, 0x8000
; GFX9-NEXT:    v_mov_b32_e32 v1, 0x7fff
; GFX9-NEXT:    v_med3_i32 v0, v0, s4, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_signed_i16_f64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cvt_i32_f64_e32 v0, s[0:1]
; GFX11-NEXT:    s_movk_i32 s0, 0x8000
; GFX11-NEXT:    v_med3_i32 v0, v0, s0, 0x7fff
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_s_signed_i16_f64:
; GFX12-ISEL:       ; %bb.0:
; GFX12-ISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-ISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-ISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-ISEL-NEXT:    v_cvt_i32_f64_e32 v0, s[0:1]
; GFX12-ISEL-NEXT:    s_movk_i32 s0, 0x8000
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    v_med3_i32 v0, v0, s0, 0x7fff
; GFX12-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_signed_i16_f64:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    v_cvt_i32_f64_e32 v0, s[0:1]
; GFX12-GI-NEXT:    v_mov_b32_e32 v1, 0xffff8000
; GFX12-GI-NEXT:    v_med3_i32 v0, v0, v1, 0x7fff
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i16 @llvm.fptosi.sat.i16.f64(double %f)
    ret i16 %x
}

define i32 @test_s_signed_i32_f64(double inreg %f) nounwind {
; GFX7-LABEL: test_s_signed_i32_f64:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_cvt_i32_f64_e32 v0, s[16:17]
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_signed_i32_f64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i32_f64_e32 v0, s[16:17]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_signed_i32_f64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cvt_i32_f64_e32 v0, s[0:1]
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_s_signed_i32_f64:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_cvt_i32_f64_e32 v0, s[0:1]
; GFX12-NEXT:    s_setpc_b64 s[30:31]
    %x = call i32 @llvm.fptosi.sat.i32.f64(double %f)
    ret i32 %x
}

define i64 @test_s_signed_i64_f64(double inreg %f) nounwind {
; GFX7-ISEL-LABEL: test_s_signed_i64_f64:
; GFX7-ISEL:       ; %bb.0:
; GFX7-ISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT:    v_trunc_f64_e32 v[0:1], s[16:17]
; GFX7-ISEL-NEXT:    s_movk_i32 s4, 0xffe0
; GFX7-ISEL-NEXT:    s_mov_b32 s5, 0xc1f00000
; GFX7-ISEL-NEXT:    v_mov_b32_e32 v4, 0
; GFX7-ISEL-NEXT:    v_mov_b32_e32 v5, 0xc3e00000
; GFX7-ISEL-NEXT:    v_mov_b32_e32 v6, -1
; GFX7-ISEL-NEXT:    v_mov_b32_e32 v7, 0x43dfffff
; GFX7-ISEL-NEXT:    v_cmp_nge_f64_e32 vcc, s[16:17], v[4:5]
; GFX7-ISEL-NEXT:    v_ldexp_f64 v[2:3], v[0:1], s4
; GFX7-ISEL-NEXT:    s_mov_b32 s4, 0
; GFX7-ISEL-NEXT:    v_cmp_u_f64_e64 s[6:7], s[16:17], s[16:17]
; GFX7-ISEL-NEXT:    v_bfrev_b32_e32 v8, 1
; GFX7-ISEL-NEXT:    v_floor_f64_e32 v[2:3], v[2:3]
; GFX7-ISEL-NEXT:    v_fma_f64 v[0:1], v[2:3], s[4:5], v[0:1]
; GFX7-ISEL-NEXT:    v_cmp_gt_f64_e64 s[4:5], s[16:17], v[6:7]
; GFX7-ISEL-NEXT:    v_cvt_i32_f64_e32 v9, v[2:3]
; GFX7-ISEL-NEXT:    v_bfrev_b32_e32 v2, -2
; GFX7-ISEL-NEXT:    v_cndmask_b32_e32 v3, v9, v8, vcc
; GFX7-ISEL-NEXT:    v_cvt_u32_f64_e32 v0, v[0:1]
; GFX7-ISEL-NEXT:    v_cndmask_b32_e64 v2, v3, v2, s[4:5]
; GFX7-ISEL-NEXT:    v_cndmask_b32_e64 v1, v2, 0, s[6:7]
; GFX7-ISEL-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX7-ISEL-NEXT:    v_cndmask_b32_e64 v0, v0, -1, s[4:5]
; GFX7-ISEL-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[6:7]
; GFX7-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_s_signed_i64_f64:
; GFX7-GI:       ; %bb.0:
; GFX7-GI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT:    v_trunc_f64_e32 v[0:1], s[16:17]
; GFX7-GI-NEXT:    v_mov_b32_e32 v2, 0
; GFX7-GI-NEXT:    v_mov_b32_e32 v3, 0x3df00000
; GFX7-GI-NEXT:    v_mov_b32_e32 v4, 0
; GFX7-GI-NEXT:    v_mov_b32_e32 v5, 0xc1f00000
; GFX7-GI-NEXT:    v_cmp_u_f64_e64 s[6:7], s[16:17], s[16:17]
; GFX7-GI-NEXT:    v_mul_f64 v[2:3], v[0:1], v[2:3]
; GFX7-GI-NEXT:    v_floor_f64_e32 v[2:3], v[2:3]
; GFX7-GI-NEXT:    v_fma_f64 v[0:1], v[2:3], v[4:5], v[0:1]
; GFX7-GI-NEXT:    v_mov_b32_e32 v4, -1
; GFX7-GI-NEXT:    v_mov_b32_e32 v5, 0x43dfffff
; GFX7-GI-NEXT:    v_cmp_gt_f64_e64 s[4:5], s[16:17], v[4:5]
; GFX7-GI-NEXT:    v_cvt_u32_f64_e32 v6, v[0:1]
; GFX7-GI-NEXT:    v_mov_b32_e32 v0, 0
; GFX7-GI-NEXT:    v_mov_b32_e32 v1, 0xc3e00000
; GFX7-GI-NEXT:    v_cmp_nge_f64_e32 vcc, s[16:17], v[0:1]
; GFX7-GI-NEXT:    v_cvt_i32_f64_e32 v1, v[2:3]
; GFX7-GI-NEXT:    v_bfrev_b32_e32 v2, 1
; GFX7-GI-NEXT:    v_bfrev_b32_e32 v3, -2
; GFX7-GI-NEXT:    v_cndmask_b32_e64 v0, v6, 0, vcc
; GFX7-GI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX7-GI-NEXT:    v_cndmask_b32_e64 v0, v0, -1, s[4:5]
; GFX7-GI-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[4:5]
; GFX7-GI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[6:7]
; GFX7-GI-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s[6:7]
; GFX7-GI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_signed_i64_f64:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_trunc_f64_e32 v[0:1], s[16:17]
; GFX9-NEXT:    s_movk_i32 s4, 0xffe0
; GFX9-NEXT:    s_mov_b32 s5, 0xc1f00000
; GFX9-NEXT:    v_mov_b32_e32 v4, 0
; GFX9-NEXT:    v_mov_b32_e32 v5, 0xc3e00000
; GFX9-NEXT:    v_mov_b32_e32 v6, -1
; GFX9-NEXT:    v_mov_b32_e32 v7, 0x43dfffff
; GFX9-NEXT:    v_cmp_nge_f64_e32 vcc, s[16:17], v[4:5]
; GFX9-NEXT:    v_ldexp_f64 v[2:3], v[0:1], s4
; GFX9-NEXT:    s_mov_b32 s4, 0
; GFX9-NEXT:    v_cmp_u_f64_e64 s[6:7], s[16:17], s[16:17]
; GFX9-NEXT:    v_bfrev_b32_e32 v8, 1
; GFX9-NEXT:    v_floor_f64_e32 v[2:3], v[2:3]
; GFX9-NEXT:    v_fma_f64 v[0:1], v[2:3], s[4:5], v[0:1]
; GFX9-NEXT:    v_cmp_gt_f64_e64 s[4:5], s[16:17], v[6:7]
; GFX9-NEXT:    v_cvt_i32_f64_e32 v9, v[2:3]
; GFX9-NEXT:    v_bfrev_b32_e32 v2, -2
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v9, v8, vcc
; GFX9-NEXT:    v_cvt_u32_f64_e32 v0, v[0:1]
; GFX9-NEXT:    v_cndmask_b32_e64 v2, v3, v2, s[4:5]
; GFX9-NEXT:    v_cndmask_b32_e64 v1, v2, 0, s[6:7]
; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, -1, s[4:5]
; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[6:7]
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_signed_i64_f64:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_trunc_f64_e32 v[0:1], s[0:1]
; GFX11-NEXT:    v_cmp_nle_f64_e64 s4, 0xc3e00000, s[0:1]
; GFX11-NEXT:    s_mov_b32 s2, -1
; GFX11-NEXT:    s_mov_b32 s3, 0x43dfffff
; GFX11-NEXT:    v_cmp_gt_f64_e64 s2, s[0:1], s[2:3]
; GFX11-NEXT:    v_cmp_u_f64_e64 s0, s[0:1], s[0:1]
; GFX11-NEXT:    v_ldexp_f64 v[2:3], v[0:1], 0xffffffe0
; GFX11-NEXT:    v_floor_f64_e32 v[2:3], v[2:3]
; GFX11-NEXT:    v_fma_f64 v[0:1], 0xc1f00000, v[2:3], v[0:1]
; GFX11-NEXT:    v_cvt_i32_f64_e32 v2, v[2:3]
; GFX11-NEXT:    v_cvt_u32_f64_e32 v0, v[0:1]
; GFX11-NEXT:    v_cndmask_b32_e64 v1, v2, 0x80000000, s4
; GFX11-NEXT:    v_cndmask_b32_e64 v1, v1, 0x7fffffff, s2
; GFX11-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s0
; GFX11-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s4
; GFX11-NEXT:    v_cndmask_b32_e64 v0, v0, -1, s2
; GFX11-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_s_signed_i64_f64:
; GFX12-ISEL:       ; %bb.0:
; GFX12-ISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-ISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-ISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-ISEL-NEXT:    v_trunc_f64_e32 v[0:1], s[0:1]
; GFX12-ISEL-NEXT:    v_cmp_nle_f64_e64 s4, 0xc3e00000, s[0:1]
; GFX12-ISEL-NEXT:    s_mov_b32 s2, -1
; GFX12-ISEL-NEXT:    s_mov_b32 s3, 0x43dfffff
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    v_cmp_gt_f64_e64 s2, s[0:1], s[2:3]
; GFX12-ISEL-NEXT:    v_cmp_u_f64_e64 s0, s[0:1], s[0:1]
; GFX12-ISEL-NEXT:    v_ldexp_f64 v[2:3], v[0:1], 0xffffffe0
; GFX12-ISEL-NEXT:    v_floor_f64_e32 v[2:3], v[2:3]
; GFX12-ISEL-NEXT:    v_fma_f64 v[0:1], 0xc1f00000, v[2:3], v[0:1]
; GFX12-ISEL-NEXT:    v_cvt_i32_f64_e32 v2, v[2:3]
; GFX12-ISEL-NEXT:    v_cvt_u32_f64_e32 v0, v[0:1]
; GFX12-ISEL-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX12-ISEL-NEXT:    v_cndmask_b32_e64 v1, v2, 0x80000000, s4
; GFX12-ISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0x7fffffff, s2
; GFX12-ISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s0
; GFX12-ISEL-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s4
; GFX12-ISEL-NEXT:    v_cndmask_b32_e64 v0, v0, -1, s2
; GFX12-ISEL-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s0
; GFX12-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_signed_i64_f64:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    v_trunc_f64_e32 v[0:1], s[0:1]
; GFX12-GI-NEXT:    v_cmp_nle_f64_e64 s2, 0xc3e00000, s[0:1]
; GFX12-GI-NEXT:    v_mul_f64_e32 v[2:3], 0x3df00000, v[0:1]
; GFX12-GI-NEXT:    v_floor_f64_e32 v[2:3], v[2:3]
; GFX12-GI-NEXT:    v_fma_f64 v[0:1], 0xc1f00000, v[2:3], v[0:1]
; GFX12-GI-NEXT:    v_cvt_i32_f64_e32 v2, v[2:3]
; GFX12-GI-NEXT:    v_cvt_u32_f64_e32 v4, v[0:1]
; GFX12-GI-NEXT:    v_dual_mov_b32 v0, -1 :: v_dual_mov_b32 v1, 0x43dfffff
; GFX12-GI-NEXT:    v_cmp_gt_f64_e32 vcc_lo, s[0:1], v[0:1]
; GFX12-GI-NEXT:    v_cmp_u_f64_e64 s0, s[0:1], s[0:1]
; GFX12-GI-NEXT:    s_wait_alu depctr_va_sdst(0)
; GFX12-GI-NEXT:    v_cndmask_b32_e64 v1, v2, 0x80000000, s2
; GFX12-GI-NEXT:    v_cndmask_b32_e64 v3, v4, 0, s2
; GFX12-GI-NEXT:    s_wait_alu depctr_va_vcc(0)
; GFX12-GI-NEXT:    v_cndmask_b32_e64 v0, v3, -1, vcc_lo
; GFX12-GI-NEXT:    v_cndmask_b32_e64 v1, v1, 0x7fffffff, vcc_lo
; GFX12-GI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s0
; GFX12-GI-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s0
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i64 @llvm.fptosi.sat.i64.f64(double %f)
    ret i64 %x
}

;
; 16-bit float to signed integer
;

declare   i1 @llvm.fptosi.sat.i1.f16  (half)
declare   i8 @llvm.fptosi.sat.i8.f16  (half)
declare  i16 @llvm.fptosi.sat.i16.f16 (half)
declare  i32 @llvm.fptosi.sat.i32.f16 (half)
declare  i64 @llvm.fptosi.sat.i64.f16 (half)

define i1 @test_signed_i1_f16(half %f) nounwind {
; GFX7-LABEL: test_signed_i1_f16:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX7-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_signed_i1_f16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i16_f16_e32 v0, v0
; GFX9-NEXT:    v_med3_i16 v0, v0, -1, 0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_signed_i1_f16:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cvt_i16_f16_e32 v0, v0
; GFX11-FAKE16-NEXT:    v_med3_i16 v0, v0, -1, 0
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: test_signed_i1_f16:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cvt_i16_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT:    v_med3_i16 v0.l, v0.l, -1, 0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_signed_i1_f16:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cvt_i16_f16_e32 v0, v0
; GFX12-FAKE16-NEXT:    v_med3_i16 v0, v0, -1, 0
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_signed_i1_f16:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cvt_i16_f16_e32 v0.l, v0.l
; GFX12-TRUE16-NEXT:    v_med3_i16 v0.l, v0.l, -1, 0
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_signed_i1_f16:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
; GFX12-GI-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX12-GI-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i1 @llvm.fptosi.sat.i1.f16(half %f)
    ret i1 %x
}

define i8 @test_signed_i8_f16(half %f) nounwind {
; GFX7-ISEL-LABEL: test_signed_i8_f16:
; GFX7-ISEL:       ; %bb.0:
; GFX7-ISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX7-ISEL-NEXT:    s_movk_i32 s4, 0xff80
; GFX7-ISEL-NEXT:    v_mov_b32_e32 v1, 0x7f
; GFX7-ISEL-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-ISEL-NEXT:    v_med3_i32 v0, v0, s4, v1
; GFX7-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_signed_i8_f16:
; GFX7-GI:       ; %bb.0:
; GFX7-GI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX7-GI-NEXT:    v_mov_b32_e32 v1, 0x7f
; GFX7-GI-NEXT:    v_mov_b32_e32 v2, 0xffffff80
; GFX7-GI-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-GI-NEXT:    v_med3_i32 v0, v0, v2, v1
; GFX7-GI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_signed_i8_f16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i16_f16_e32 v0, v0
; GFX9-NEXT:    s_movk_i32 s4, 0xff80
; GFX9-NEXT:    v_mov_b32_e32 v1, 0x7f
; GFX9-NEXT:    v_med3_i16 v0, v0, s4, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_signed_i8_f16:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cvt_i16_f16_e32 v0, v0
; GFX11-FAKE16-NEXT:    s_movk_i32 s0, 0xff80
; GFX11-FAKE16-NEXT:    v_med3_i16 v0, v0, s0, 0x7f
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: test_signed_i8_f16:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cvt_i16_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, 0xff80
; GFX11-TRUE16-NEXT:    v_med3_i16 v0.l, v0.l, v0.h, 0x7f
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_signed_i8_f16:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cvt_i16_f16_e32 v0, v0
; GFX12-FAKE16-NEXT:    s_movk_i32 s0, 0xff80
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT:    v_med3_i16 v0, v0, s0, 0x7f
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_signed_i8_f16:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cvt_i16_f16_e32 v0.l, v0.l
; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, 0xff80
; GFX12-TRUE16-NEXT:    v_med3_i16 v0.l, v0.l, v0.h, 0x7f
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_signed_i8_f16:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
; GFX12-GI-NEXT:    v_mov_b32_e32 v1, 0xffffff80
; GFX12-GI-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX12-GI-NEXT:    v_med3_i32 v0, v0, v1, 0x7f
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i8 @llvm.fptosi.sat.i8.f16(half %f)
    ret i8 %x
}

define i16 @test_signed_i16_f16(half %f) nounwind {
; GFX7-ISEL-LABEL: test_signed_i16_f16:
; GFX7-ISEL:       ; %bb.0:
; GFX7-ISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX7-ISEL-NEXT:    s_movk_i32 s4, 0x8000
; GFX7-ISEL-NEXT:    v_mov_b32_e32 v1, 0x7fff
; GFX7-ISEL-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-ISEL-NEXT:    v_med3_i32 v0, v0, s4, v1
; GFX7-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_signed_i16_f16:
; GFX7-GI:       ; %bb.0:
; GFX7-GI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX7-GI-NEXT:    v_mov_b32_e32 v1, 0x7fff
; GFX7-GI-NEXT:    v_mov_b32_e32 v2, 0xffff8000
; GFX7-GI-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-GI-NEXT:    v_med3_i32 v0, v0, v2, v1
; GFX7-GI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_signed_i16_f16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i16_f16_e32 v0, v0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_signed_i16_f16:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cvt_i16_f16_e32 v0, v0
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: test_signed_i16_f16:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cvt_i16_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_signed_i16_f16:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cvt_i16_f16_e32 v0, v0
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_signed_i16_f16:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cvt_i16_f16_e32 v0.l, v0.l
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_signed_i16_f16:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    v_cvt_i16_f16_e32 v0.l, v0.l
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i16 @llvm.fptosi.sat.i16.f16(half %f)
    ret i16 %x
}

define i32 @test_signed_i32_f16(half %f) nounwind {
; GFX7-LABEL: test_signed_i32_f16:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX7-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_signed_i32_f16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX9-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_signed_i32_f16:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX11-FAKE16-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: test_signed_i32_f16:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
; GFX11-TRUE16-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_signed_i32_f16:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX12-FAKE16-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_signed_i32_f16:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
; GFX12-TRUE16-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_signed_i32_f16:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
; GFX12-GI-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i32 @llvm.fptosi.sat.i32.f16(half %f)
    ret i32 %x
}

define i64 @test_signed_i64_f16(half %f) nounwind {
; GFX7-ISEL-LABEL: test_signed_i64_f16:
; GFX7-ISEL:       ; %bb.0:
; GFX7-ISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX7-ISEL-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-ISEL-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
; GFX7-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_signed_i64_f16:
; GFX7-GI:       ; %bb.0:
; GFX7-GI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX7-GI-NEXT:    v_mov_b32_e32 v1, 0
; GFX7-GI-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-GI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_signed_i64_f16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX9-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX9-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_signed_i64_f16:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX11-FAKE16-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX11-FAKE16-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: test_signed_i64_f16:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
; GFX11-TRUE16-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX11-TRUE16-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_signed_i64_f16:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cvt_f32_f16_e32 v0, v0
; GFX12-FAKE16-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX12-FAKE16-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_signed_i64_f16:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
; GFX12-TRUE16-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX12-TRUE16-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_signed_i64_f16:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    v_cvt_f32_f16_e32 v0, v0.l
; GFX12-GI-NEXT:    v_mov_b32_e32 v1, 0
; GFX12-GI-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i64 @llvm.fptosi.sat.i64.f16(half %f)
    ret i64 %x
}

define i1 @test_s_signed_i1_f16(half inreg %f) nounwind {
; GFX7-LABEL: test_s_signed_i1_f16:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, s16
; GFX7-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_signed_i1_f16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i16_f16_e32 v0, s16
; GFX9-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX9-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_s_signed_i1_f16:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cvt_i16_f16_e32 v0, s0
; GFX11-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX11-FAKE16-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: test_s_signed_i1_f16:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cvt_i16_f16_e32 v0.l, s0
; GFX11-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX11-TRUE16-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_s_signed_i1_f16:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cvt_i16_f16_e32 v0, s0
; GFX12-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX12-FAKE16-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_s_signed_i1_f16:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cvt_i16_f16_e32 v0.l, s0
; GFX12-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX12-TRUE16-NEXT:    v_med3_i32 v0, v0, -1, 0
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_signed_i1_f16:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    s_cvt_f32_f16 s0, s0
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_cvt_i32_f32 s0, s0
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_min_i32 s0, s0, 0
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_max_i32 s0, s0, -1
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i1 @llvm.fptosi.sat.i1.f16(half %f)
    ret i1 %x
}

define i8 @test_s_signed_i8_f16(half inreg %f) nounwind {
; GFX7-ISEL-LABEL: test_s_signed_i8_f16:
; GFX7-ISEL:       ; %bb.0:
; GFX7-ISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT:    v_cvt_f32_f16_e32 v0, s16
; GFX7-ISEL-NEXT:    s_movk_i32 s4, 0xff80
; GFX7-ISEL-NEXT:    v_mov_b32_e32 v1, 0x7f
; GFX7-ISEL-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-ISEL-NEXT:    v_med3_i32 v0, v0, s4, v1
; GFX7-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_s_signed_i8_f16:
; GFX7-GI:       ; %bb.0:
; GFX7-GI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT:    v_cvt_f32_f16_e32 v0, s16
; GFX7-GI-NEXT:    v_mov_b32_e32 v1, 0x7f
; GFX7-GI-NEXT:    v_mov_b32_e32 v2, 0xffffff80
; GFX7-GI-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-GI-NEXT:    v_med3_i32 v0, v0, v2, v1
; GFX7-GI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_signed_i8_f16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i16_f16_e32 v0, s16
; GFX9-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX9-NEXT:    s_movk_i32 s4, 0xff80
; GFX9-NEXT:    v_mov_b32_e32 v1, 0x7f
; GFX9-NEXT:    v_med3_i32 v0, v0, s4, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_s_signed_i8_f16:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cvt_i16_f16_e32 v0, s0
; GFX11-FAKE16-NEXT:    s_movk_i32 s0, 0xff80
; GFX11-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX11-FAKE16-NEXT:    v_med3_i32 v0, v0, s0, 0x7f
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: test_s_signed_i8_f16:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cvt_i16_f16_e32 v0.l, s0
; GFX11-TRUE16-NEXT:    s_movk_i32 s0, 0xff80
; GFX11-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX11-TRUE16-NEXT:    v_med3_i32 v0, v0, s0, 0x7f
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_s_signed_i8_f16:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cvt_i16_f16_e32 v0, s0
; GFX12-FAKE16-NEXT:    s_movk_i32 s0, 0xff80
; GFX12-FAKE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX12-FAKE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT:    v_med3_i32 v0, v0, s0, 0x7f
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_s_signed_i8_f16:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cvt_i16_f16_e32 v0.l, s0
; GFX12-TRUE16-NEXT:    s_movk_i32 s0, 0xff80
; GFX12-TRUE16-NEXT:    v_bfe_i32 v0, v0, 0, 16
; GFX12-TRUE16-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT:    v_med3_i32 v0, v0, s0, 0x7f
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_signed_i8_f16:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    s_cvt_f32_f16 s0, s0
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_cvt_i32_f32 s0, s0
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_min_i32 s0, s0, 0x7f
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_max_i32 s0, s0, 0xffffff80
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i8 @llvm.fptosi.sat.i8.f16(half %f)
    ret i8 %x
}

define i16 @test_s_signed_i16_f16(half inreg %f) nounwind {
; GFX7-ISEL-LABEL: test_s_signed_i16_f16:
; GFX7-ISEL:       ; %bb.0:
; GFX7-ISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT:    v_cvt_f32_f16_e32 v0, s16
; GFX7-ISEL-NEXT:    s_movk_i32 s4, 0x8000
; GFX7-ISEL-NEXT:    v_mov_b32_e32 v1, 0x7fff
; GFX7-ISEL-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-ISEL-NEXT:    v_med3_i32 v0, v0, s4, v1
; GFX7-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_s_signed_i16_f16:
; GFX7-GI:       ; %bb.0:
; GFX7-GI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT:    v_cvt_f32_f16_e32 v0, s16
; GFX7-GI-NEXT:    v_mov_b32_e32 v1, 0x7fff
; GFX7-GI-NEXT:    v_mov_b32_e32 v2, 0xffff8000
; GFX7-GI-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-GI-NEXT:    v_med3_i32 v0, v0, v2, v1
; GFX7-GI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_signed_i16_f16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_i16_f16_e32 v0, s16
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_s_signed_i16_f16:
; GFX11-FAKE16:       ; %bb.0:
; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT:    v_cvt_i16_f16_e32 v0, s0
; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: test_s_signed_i16_f16:
; GFX11-TRUE16:       ; %bb.0:
; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT:    v_cvt_i16_f16_e32 v0.l, s0
; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_s_signed_i16_f16:
; GFX12-FAKE16:       ; %bb.0:
; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT:    v_cvt_i16_f16_e32 v0, s0
; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_s_signed_i16_f16:
; GFX12-TRUE16:       ; %bb.0:
; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT:    v_cvt_i16_f16_e32 v0.l, s0
; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_signed_i16_f16:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    v_cvt_i16_f16_e32 v0.l, s0
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i16 @llvm.fptosi.sat.i16.f16(half %f)
    ret i16 %x
}

define i32 @test_s_signed_i32_f16(half inreg %f) nounwind {
; GFX7-LABEL: test_s_signed_i32_f16:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_cvt_f32_f16_e32 v0, s16
; GFX7-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_signed_i32_f16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_f32_f16_e32 v0, s16
; GFX9-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_signed_i32_f16:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, s0
; GFX11-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: test_s_signed_i32_f16:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    s_cvt_f32_f16 s0, s0
; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT:    s_cvt_i32_f32 s0, s0
; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-NEXT:    s_setpc_b64 s[30:31]
    %x = call i32 @llvm.fptosi.sat.i32.f16(half %f)
    ret i32 %x
}

define i64 @test_s_signed_i64_f16(half inreg %f) nounwind {
; GFX7-ISEL-LABEL: test_s_signed_i64_f16:
; GFX7-ISEL:       ; %bb.0:
; GFX7-ISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-ISEL-NEXT:    v_cvt_f32_f16_e32 v0, s16
; GFX7-ISEL-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-ISEL-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
; GFX7-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX7-GI-LABEL: test_s_signed_i64_f16:
; GFX7-GI:       ; %bb.0:
; GFX7-GI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-GI-NEXT:    v_cvt_f32_f16_e32 v0, s16
; GFX7-GI-NEXT:    v_mov_b32_e32 v1, 0
; GFX7-GI-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX7-GI-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: test_s_signed_i64_f16:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cvt_f32_f16_e32 v0, s16
; GFX9-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX9-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_signed_i64_f16:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cvt_f32_f16_e32 v0, s0
; GFX11-NEXT:    v_cvt_i32_f32_e32 v0, v0
; GFX11-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_s_signed_i64_f16:
; GFX12-ISEL:       ; %bb.0:
; GFX12-ISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-ISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-ISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-ISEL-NEXT:    s_cvt_f32_f16 s0, s0
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    s_cvt_i32_f32 s0, s0
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    s_ashr_i32 s1, s0, 31
; GFX12-ISEL-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-ISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_signed_i64_f16:
; GFX12-GI:       ; %bb.0:
; GFX12-GI-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GI-NEXT:    s_wait_expcnt 0x0
; GFX12-GI-NEXT:    s_wait_samplecnt 0x0
; GFX12-GI-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GI-NEXT:    s_wait_kmcnt 0x0
; GFX12-GI-NEXT:    s_cvt_f32_f16 s0, s0
; GFX12-GI-NEXT:    v_mov_b32_e32 v1, 0
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    s_cvt_i32_f32 s0, s0
; GFX12-GI-NEXT:    s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT:    v_mov_b32_e32 v0, s0
; GFX12-GI-NEXT:    s_setpc_b64 s[30:31]
    %x = call i64 @llvm.fptosi.sat.i64.f16(half %f)
    ret i64 %x
}