| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 |
| ; RUN: llc -O0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck --check-prefix GFX950 %s |
| ; RUN: llc -O0 -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck --check-prefix GFX90A %s |
| |
| ; Verify div/rem lowering at -O0 for operands that do or do not qualify for the |
| ; float-reciprocal fast path. |
| |
| define amdgpu_kernel void @udiv_i32_i16_no_fast_path(ptr addrspace(1) %out, i32 %input) { |
| ; GFX950-LABEL: udiv_i32_i16_no_fast_path: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_load_dword s0, s[4:5], 0x2c |
| ; GFX950-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_sext_i32_i16 s4, s2 |
| ; GFX950-NEXT: s_mov_b32 s2, 1 |
| ; GFX950-NEXT: s_or_b32 s5, s4, s2 |
| ; GFX950-NEXT: s_mov_b32 s3, 0 |
| ; GFX950-NEXT: s_sub_i32 s3, s3, s5 |
| ; GFX950-NEXT: v_cvt_f32_u32_e32 v1, s5 |
| ; GFX950-NEXT: v_rcp_iflag_f32_e32 v1, v1 |
| ; GFX950-NEXT: s_nop 0 |
| ; GFX950-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 |
| ; GFX950-NEXT: v_cvt_u32_f32_e32 v1, v1 |
| ; GFX950-NEXT: s_nop 0 |
| ; GFX950-NEXT: v_readfirstlane_b32 s6, v1 |
| ; GFX950-NEXT: s_mul_i32 s6, s3, s6 |
| ; GFX950-NEXT: v_readfirstlane_b32 s3, v1 |
| ; GFX950-NEXT: s_mul_hi_u32 s6, s3, s6 |
| ; GFX950-NEXT: v_readfirstlane_b32 s3, v1 |
| ; GFX950-NEXT: s_add_i32 s3, s3, s6 |
| ; GFX950-NEXT: s_mul_hi_u32 s6, s4, s3 |
| ; GFX950-NEXT: s_add_i32 s3, s6, s2 |
| ; GFX950-NEXT: s_mul_i32 s7, s6, s5 |
| ; GFX950-NEXT: s_sub_i32 s7, s4, s7 |
| ; GFX950-NEXT: s_sub_i32 s4, s7, s5 |
| ; GFX950-NEXT: s_cmp_ge_u32 s7, s5 |
| ; GFX950-NEXT: s_cselect_b32 s4, s4, s7 |
| ; GFX950-NEXT: s_cselect_b32 s3, s3, s6 |
| ; GFX950-NEXT: s_add_i32 s2, s3, s2 |
| ; GFX950-NEXT: s_cmp_ge_u32 s4, s5 |
| ; GFX950-NEXT: s_cselect_b32 s2, s2, s3 |
| ; GFX950-NEXT: v_mov_b32_e32 v1, s2 |
| ; GFX950-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX950-NEXT: s_endpgm |
| ; |
| ; GFX90A-LABEL: udiv_i32_i16_no_fast_path: |
| ; GFX90A: ; %bb.0: |
| ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_load_dword s0, s[4:5], 0x2c |
| ; GFX90A-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX90A-NEXT: s_load_dword s2, s[4:5], 0x2c |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_sext_i32_i16 s4, s2 |
| ; GFX90A-NEXT: s_mov_b32 s2, 1 |
| ; GFX90A-NEXT: s_or_b32 s5, s4, s2 |
| ; GFX90A-NEXT: s_mov_b32 s3, 0 |
| ; GFX90A-NEXT: s_sub_i32 s3, s3, s5 |
| ; GFX90A-NEXT: v_cvt_f32_u32_e32 v1, s5 |
| ; GFX90A-NEXT: v_rcp_iflag_f32_e32 v1, v1 |
| ; GFX90A-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 |
| ; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1 |
| ; GFX90A-NEXT: v_readfirstlane_b32 s6, v1 |
| ; GFX90A-NEXT: s_mul_i32 s6, s3, s6 |
| ; GFX90A-NEXT: v_readfirstlane_b32 s3, v1 |
| ; GFX90A-NEXT: s_mul_hi_u32 s6, s3, s6 |
| ; GFX90A-NEXT: v_readfirstlane_b32 s3, v1 |
| ; GFX90A-NEXT: s_add_i32 s3, s3, s6 |
| ; GFX90A-NEXT: s_mul_hi_u32 s6, s4, s3 |
| ; GFX90A-NEXT: s_add_i32 s3, s6, s2 |
| ; GFX90A-NEXT: s_mul_i32 s7, s6, s5 |
| ; GFX90A-NEXT: s_sub_i32 s7, s4, s7 |
| ; GFX90A-NEXT: s_sub_i32 s4, s7, s5 |
| ; GFX90A-NEXT: s_cmp_ge_u32 s7, s5 |
| ; GFX90A-NEXT: s_cselect_b32 s4, s4, s7 |
| ; GFX90A-NEXT: s_cselect_b32 s3, s3, s6 |
| ; GFX90A-NEXT: s_add_i32 s2, s3, s2 |
| ; GFX90A-NEXT: s_cmp_ge_u32 s4, s5 |
| ; GFX90A-NEXT: s_cselect_b32 s2, s2, s3 |
| ; GFX90A-NEXT: v_mov_b32_e32 v1, s2 |
| ; GFX90A-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX90A-NEXT: s_endpgm |
| %trunc_i16 = trunc i32 %input to i16 |
| %dividend = sext i16 %trunc_i16 to i32 |
| %divisor = or i32 %dividend, 1 |
| %result = udiv i32 %dividend, %divisor |
| store i32 %result, ptr addrspace(1) %out, align 4 |
| ret void |
| } |
| |
| define amdgpu_kernel void @udiv_i32_and_i24_fast_path(ptr addrspace(1) %out, i32 %input) { |
| ; GFX950-LABEL: udiv_i32_and_i24_fast_path: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_load_dword s0, s[4:5], 0x2c |
| ; GFX950-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX950-NEXT: s_load_dword s3, s[4:5], 0x2c |
| ; GFX950-NEXT: s_mov_b32 s2, 0xffffff |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_and_b32 s5, s3, s2 |
| ; GFX950-NEXT: s_mov_b32 s3, 1 |
| ; GFX950-NEXT: s_or_b32 s4, s5, s3 |
| ; GFX950-NEXT: v_cvt_f32_u32_e64 v2, s5 |
| ; GFX950-NEXT: v_cvt_f32_u32_e64 v3, s4 |
| ; GFX950-NEXT: v_rcp_f32_e64 v1, v3 |
| ; GFX950-NEXT: s_nop 0 |
| ; GFX950-NEXT: v_mul_f32_e64 v1, v2, v1 |
| ; GFX950-NEXT: v_trunc_f32_e64 v1, v1 |
| ; GFX950-NEXT: v_fma_f32 v2, -v1, v3, v2 |
| ; GFX950-NEXT: v_cmp_ge_f32_e64 s[6:7], |v2|, |v3| |
| ; GFX950-NEXT: s_mov_b32 s4, 0 |
| ; GFX950-NEXT: s_and_b64 s[6:7], s[6:7], exec |
| ; GFX950-NEXT: s_cselect_b32 s3, s3, s4 |
| ; GFX950-NEXT: v_cvt_u32_f32_e64 v1, v1 |
| ; GFX950-NEXT: v_add_u32_e64 v1, v1, s3 |
| ; GFX950-NEXT: v_and_b32_e64 v1, v1, s2 |
| ; GFX950-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX950-NEXT: s_endpgm |
| ; |
| ; GFX90A-LABEL: udiv_i32_and_i24_fast_path: |
| ; GFX90A: ; %bb.0: |
| ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_load_dword s0, s[4:5], 0x2c |
| ; GFX90A-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX90A-NEXT: s_load_dword s3, s[4:5], 0x2c |
| ; GFX90A-NEXT: s_mov_b32 s2, 0xffffff |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_and_b32 s5, s3, s2 |
| ; GFX90A-NEXT: s_mov_b32 s3, 1 |
| ; GFX90A-NEXT: s_or_b32 s4, s5, s3 |
| ; GFX90A-NEXT: v_cvt_f32_u32_e64 v2, s5 |
| ; GFX90A-NEXT: v_cvt_f32_u32_e64 v3, s4 |
| ; GFX90A-NEXT: v_rcp_f32_e64 v1, v3 |
| ; GFX90A-NEXT: v_mul_f32_e64 v1, v2, v1 |
| ; GFX90A-NEXT: v_trunc_f32_e64 v1, v1 |
| ; GFX90A-NEXT: v_mad_f32 v2, -v1, v3, v2 |
| ; GFX90A-NEXT: v_cmp_ge_f32_e64 s[6:7], |v2|, |v3| |
| ; GFX90A-NEXT: s_mov_b32 s4, 0 |
| ; GFX90A-NEXT: s_and_b64 s[6:7], s[6:7], exec |
| ; GFX90A-NEXT: s_cselect_b32 s3, s3, s4 |
| ; GFX90A-NEXT: v_cvt_u32_f32_e64 v1, v1 |
| ; GFX90A-NEXT: v_add_u32_e64 v1, v1, s3 |
| ; GFX90A-NEXT: v_and_b32_e64 v1, v1, s2 |
| ; GFX90A-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX90A-NEXT: s_endpgm |
| %dividend = and i32 %input, u0xffffff |
| %divisor = or i32 %dividend, 1 |
| %result = udiv i32 %dividend, %divisor |
| store i32 %result, ptr addrspace(1) %out, align 4 |
| ret void |
| } |
| |
| define amdgpu_kernel void @sdiv_i32_i16_no_fast_path(ptr addrspace(1) %out, i32 %input) { |
| ; GFX950-LABEL: sdiv_i32_i16_no_fast_path: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_load_dword s0, s[4:5], 0x2c |
| ; GFX950-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_mov_b32 s3, s2 |
| ; GFX950-NEXT: s_sext_i32_i16 s5, s3 |
| ; GFX950-NEXT: s_mov_b32 s6, 0 |
| ; GFX950-NEXT: s_cmp_lt_i32 s2, s6 |
| ; GFX950-NEXT: s_mov_b32 s3, -1 |
| ; GFX950-NEXT: s_cselect_b32 s4, s3, s6 |
| ; GFX950-NEXT: s_add_i32 s2, s2, s4 |
| ; GFX950-NEXT: s_xor_b32 s7, s2, s4 |
| ; GFX950-NEXT: s_sub_i32 s2, s6, s7 |
| ; GFX950-NEXT: v_cvt_f32_u32_e32 v1, s7 |
| ; GFX950-NEXT: v_rcp_iflag_f32_e32 v1, v1 |
| ; GFX950-NEXT: s_nop 0 |
| ; GFX950-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 |
| ; GFX950-NEXT: v_cvt_u32_f32_e32 v1, v1 |
| ; GFX950-NEXT: s_nop 0 |
| ; GFX950-NEXT: v_readfirstlane_b32 s8, v1 |
| ; GFX950-NEXT: s_mul_i32 s8, s2, s8 |
| ; GFX950-NEXT: v_readfirstlane_b32 s2, v1 |
| ; GFX950-NEXT: s_mul_hi_u32 s8, s2, s8 |
| ; GFX950-NEXT: v_readfirstlane_b32 s2, v1 |
| ; GFX950-NEXT: s_add_i32 s2, s2, s8 |
| ; GFX950-NEXT: s_cmp_lt_i32 s5, s6 |
| ; GFX950-NEXT: s_cselect_b32 s3, s3, s6 |
| ; GFX950-NEXT: s_add_i32 s5, s5, s3 |
| ; GFX950-NEXT: s_xor_b32 s6, s5, s3 |
| ; GFX950-NEXT: s_mul_hi_u32 s8, s6, s2 |
| ; GFX950-NEXT: s_mov_b32 s2, 1 |
| ; GFX950-NEXT: s_add_i32 s5, s8, s2 |
| ; GFX950-NEXT: s_mul_i32 s9, s8, s7 |
| ; GFX950-NEXT: s_sub_i32 s9, s6, s9 |
| ; GFX950-NEXT: s_sub_i32 s6, s9, s7 |
| ; GFX950-NEXT: s_cmp_ge_u32 s9, s7 |
| ; GFX950-NEXT: s_cselect_b32 s6, s6, s9 |
| ; GFX950-NEXT: s_cselect_b32 s5, s5, s8 |
| ; GFX950-NEXT: s_add_i32 s2, s5, s2 |
| ; GFX950-NEXT: s_cmp_ge_u32 s6, s7 |
| ; GFX950-NEXT: s_cselect_b32 s2, s2, s5 |
| ; GFX950-NEXT: s_xor_b32 s3, s3, s4 |
| ; GFX950-NEXT: s_xor_b32 s2, s2, s3 |
| ; GFX950-NEXT: s_sub_i32 s2, s2, s3 |
| ; GFX950-NEXT: v_mov_b32_e32 v1, s2 |
| ; GFX950-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX950-NEXT: s_endpgm |
| ; |
| ; GFX90A-LABEL: sdiv_i32_i16_no_fast_path: |
| ; GFX90A: ; %bb.0: |
| ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_load_dword s0, s[4:5], 0x2c |
| ; GFX90A-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX90A-NEXT: s_load_dword s2, s[4:5], 0x2c |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_mov_b32 s3, s2 |
| ; GFX90A-NEXT: s_sext_i32_i16 s5, s3 |
| ; GFX90A-NEXT: s_mov_b32 s6, 0 |
| ; GFX90A-NEXT: s_cmp_lt_i32 s2, s6 |
| ; GFX90A-NEXT: s_mov_b32 s3, -1 |
| ; GFX90A-NEXT: s_cselect_b32 s4, s3, s6 |
| ; GFX90A-NEXT: s_add_i32 s2, s2, s4 |
| ; GFX90A-NEXT: s_xor_b32 s7, s2, s4 |
| ; GFX90A-NEXT: s_sub_i32 s2, s6, s7 |
| ; GFX90A-NEXT: v_cvt_f32_u32_e32 v1, s7 |
| ; GFX90A-NEXT: v_rcp_iflag_f32_e32 v1, v1 |
| ; GFX90A-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 |
| ; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1 |
| ; GFX90A-NEXT: v_readfirstlane_b32 s8, v1 |
| ; GFX90A-NEXT: s_mul_i32 s8, s2, s8 |
| ; GFX90A-NEXT: v_readfirstlane_b32 s2, v1 |
| ; GFX90A-NEXT: s_mul_hi_u32 s8, s2, s8 |
| ; GFX90A-NEXT: v_readfirstlane_b32 s2, v1 |
| ; GFX90A-NEXT: s_add_i32 s2, s2, s8 |
| ; GFX90A-NEXT: s_cmp_lt_i32 s5, s6 |
| ; GFX90A-NEXT: s_cselect_b32 s3, s3, s6 |
| ; GFX90A-NEXT: s_add_i32 s5, s5, s3 |
| ; GFX90A-NEXT: s_xor_b32 s6, s5, s3 |
| ; GFX90A-NEXT: s_mul_hi_u32 s8, s6, s2 |
| ; GFX90A-NEXT: s_mov_b32 s2, 1 |
| ; GFX90A-NEXT: s_add_i32 s5, s8, s2 |
| ; GFX90A-NEXT: s_mul_i32 s9, s8, s7 |
| ; GFX90A-NEXT: s_sub_i32 s9, s6, s9 |
| ; GFX90A-NEXT: s_sub_i32 s6, s9, s7 |
| ; GFX90A-NEXT: s_cmp_ge_u32 s9, s7 |
| ; GFX90A-NEXT: s_cselect_b32 s6, s6, s9 |
| ; GFX90A-NEXT: s_cselect_b32 s5, s5, s8 |
| ; GFX90A-NEXT: s_add_i32 s2, s5, s2 |
| ; GFX90A-NEXT: s_cmp_ge_u32 s6, s7 |
| ; GFX90A-NEXT: s_cselect_b32 s2, s2, s5 |
| ; GFX90A-NEXT: s_xor_b32 s3, s3, s4 |
| ; GFX90A-NEXT: s_xor_b32 s2, s2, s3 |
| ; GFX90A-NEXT: s_sub_i32 s2, s2, s3 |
| ; GFX90A-NEXT: v_mov_b32_e32 v1, s2 |
| ; GFX90A-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX90A-NEXT: s_endpgm |
| %trunc_i16 = trunc i32 %input to i16 |
| %dividend = sext i16 %trunc_i16 to i32 |
| %result = sdiv i32 %dividend, %input |
| store i32 %result, ptr addrspace(1) %out, align 4 |
| ret void |
| } |
| |
| define amdgpu_kernel void @sdiv_i32_i16_fast_path(ptr addrspace(1) %out, i32 %input) { |
| ; GFX950-LABEL: sdiv_i32_i16_fast_path: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_load_dword s0, s[4:5], 0x2c |
| ; GFX950-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_sext_i32_i16 s2, s2 |
| ; GFX950-NEXT: s_mov_b32 s3, 1 |
| ; GFX950-NEXT: s_or_b32 s6, s2, s3 |
| ; GFX950-NEXT: v_cvt_f32_i32_e64 v3, s6 |
| ; GFX950-NEXT: v_rcp_f32_e64 v1, v3 |
| ; GFX950-NEXT: v_cvt_f32_i32_e64 v2, s2 |
| ; GFX950-NEXT: v_mul_f32_e64 v1, v2, v1 |
| ; GFX950-NEXT: v_trunc_f32_e64 v1, v1 |
| ; GFX950-NEXT: v_fma_f32 v2, -v1, v3, v2 |
| ; GFX950-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, |v3| |
| ; GFX950-NEXT: s_xor_b32 s2, s2, s6 |
| ; GFX950-NEXT: s_mov_b32 s6, 30 |
| ; GFX950-NEXT: s_ashr_i32 s2, s2, s6 |
| ; GFX950-NEXT: s_or_b32 s2, s2, s3 |
| ; GFX950-NEXT: s_mov_b32 s3, 0 |
| ; GFX950-NEXT: s_and_b64 s[4:5], s[4:5], exec |
| ; GFX950-NEXT: s_cselect_b32 s2, s2, s3 |
| ; GFX950-NEXT: v_cvt_i32_f32_e64 v1, v1 |
| ; GFX950-NEXT: v_add_u32_e64 v1, v1, s2 |
| ; GFX950-NEXT: v_bfe_i32 v1, v1, 0, 16 |
| ; GFX950-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX950-NEXT: s_endpgm |
| ; |
| ; GFX90A-LABEL: sdiv_i32_i16_fast_path: |
| ; GFX90A: ; %bb.0: |
| ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_load_dword s0, s[4:5], 0x2c |
| ; GFX90A-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX90A-NEXT: s_load_dword s2, s[4:5], 0x2c |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_sext_i32_i16 s2, s2 |
| ; GFX90A-NEXT: s_mov_b32 s3, 1 |
| ; GFX90A-NEXT: s_or_b32 s6, s2, s3 |
| ; GFX90A-NEXT: v_cvt_f32_i32_e64 v3, s6 |
| ; GFX90A-NEXT: v_rcp_f32_e64 v1, v3 |
| ; GFX90A-NEXT: v_cvt_f32_i32_e64 v2, s2 |
| ; GFX90A-NEXT: v_mul_f32_e64 v1, v2, v1 |
| ; GFX90A-NEXT: v_trunc_f32_e64 v1, v1 |
| ; GFX90A-NEXT: v_mad_f32 v2, -v1, v3, v2 |
| ; GFX90A-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, |v3| |
| ; GFX90A-NEXT: s_xor_b32 s2, s2, s6 |
| ; GFX90A-NEXT: s_mov_b32 s6, 30 |
| ; GFX90A-NEXT: s_ashr_i32 s2, s2, s6 |
| ; GFX90A-NEXT: s_or_b32 s2, s2, s3 |
| ; GFX90A-NEXT: s_mov_b32 s3, 0 |
| ; GFX90A-NEXT: s_and_b64 s[4:5], s[4:5], exec |
| ; GFX90A-NEXT: s_cselect_b32 s2, s2, s3 |
| ; GFX90A-NEXT: v_cvt_i32_f32_e64 v1, v1 |
| ; GFX90A-NEXT: v_add_u32_e64 v1, v1, s2 |
| ; GFX90A-NEXT: v_bfe_i32 v1, v1, 0, 16 |
| ; GFX90A-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX90A-NEXT: s_endpgm |
| %trunc_i16 = trunc i32 %input to i16 |
| %dividend = sext i16 %trunc_i16 to i32 |
| %divisor = or i32 %dividend, 1 |
| %result = sdiv i32 %dividend, %divisor |
| store i32 %result, ptr addrspace(1) %out, align 4 |
| ret void |
| } |
| |
| define amdgpu_kernel void @urem_i32_i16_no_fast_path(ptr addrspace(1) %out, i32 %input) { |
| ; GFX950-LABEL: urem_i32_i16_no_fast_path: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_load_dword s0, s[4:5], 0x2c |
| ; GFX950-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_sext_i32_i16 s2, s2 |
| ; GFX950-NEXT: s_mov_b32 s3, 1 |
| ; GFX950-NEXT: s_or_b32 s4, s2, s3 |
| ; GFX950-NEXT: s_mov_b32 s3, 0 |
| ; GFX950-NEXT: s_sub_i32 s3, s3, s4 |
| ; GFX950-NEXT: v_cvt_f32_u32_e32 v1, s4 |
| ; GFX950-NEXT: v_rcp_iflag_f32_e32 v1, v1 |
| ; GFX950-NEXT: s_nop 0 |
| ; GFX950-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 |
| ; GFX950-NEXT: v_cvt_u32_f32_e32 v1, v1 |
| ; GFX950-NEXT: s_nop 0 |
| ; GFX950-NEXT: v_readfirstlane_b32 s5, v1 |
| ; GFX950-NEXT: s_mul_i32 s5, s3, s5 |
| ; GFX950-NEXT: v_readfirstlane_b32 s3, v1 |
| ; GFX950-NEXT: s_mul_hi_u32 s5, s3, s5 |
| ; GFX950-NEXT: v_readfirstlane_b32 s3, v1 |
| ; GFX950-NEXT: s_add_i32 s3, s3, s5 |
| ; GFX950-NEXT: s_mul_hi_u32 s3, s2, s3 |
| ; GFX950-NEXT: s_mul_i32 s3, s3, s4 |
| ; GFX950-NEXT: s_sub_i32 s3, s2, s3 |
| ; GFX950-NEXT: s_sub_i32 s2, s3, s4 |
| ; GFX950-NEXT: s_cmp_ge_u32 s3, s4 |
| ; GFX950-NEXT: s_cselect_b32 s3, s2, s3 |
| ; GFX950-NEXT: s_sub_i32 s2, s3, s4 |
| ; GFX950-NEXT: s_cmp_ge_u32 s3, s4 |
| ; GFX950-NEXT: s_cselect_b32 s2, s2, s3 |
| ; GFX950-NEXT: v_mov_b32_e32 v1, s2 |
| ; GFX950-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX950-NEXT: s_endpgm |
| ; |
| ; GFX90A-LABEL: urem_i32_i16_no_fast_path: |
| ; GFX90A: ; %bb.0: |
| ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_load_dword s0, s[4:5], 0x2c |
| ; GFX90A-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX90A-NEXT: s_load_dword s2, s[4:5], 0x2c |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_sext_i32_i16 s2, s2 |
| ; GFX90A-NEXT: s_mov_b32 s3, 1 |
| ; GFX90A-NEXT: s_or_b32 s4, s2, s3 |
| ; GFX90A-NEXT: s_mov_b32 s3, 0 |
| ; GFX90A-NEXT: s_sub_i32 s3, s3, s4 |
| ; GFX90A-NEXT: v_cvt_f32_u32_e32 v1, s4 |
| ; GFX90A-NEXT: v_rcp_iflag_f32_e32 v1, v1 |
| ; GFX90A-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 |
| ; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1 |
| ; GFX90A-NEXT: v_readfirstlane_b32 s5, v1 |
| ; GFX90A-NEXT: s_mul_i32 s5, s3, s5 |
| ; GFX90A-NEXT: v_readfirstlane_b32 s3, v1 |
| ; GFX90A-NEXT: s_mul_hi_u32 s5, s3, s5 |
| ; GFX90A-NEXT: v_readfirstlane_b32 s3, v1 |
| ; GFX90A-NEXT: s_add_i32 s3, s3, s5 |
| ; GFX90A-NEXT: s_mul_hi_u32 s3, s2, s3 |
| ; GFX90A-NEXT: s_mul_i32 s3, s3, s4 |
| ; GFX90A-NEXT: s_sub_i32 s3, s2, s3 |
| ; GFX90A-NEXT: s_sub_i32 s2, s3, s4 |
| ; GFX90A-NEXT: s_cmp_ge_u32 s3, s4 |
| ; GFX90A-NEXT: s_cselect_b32 s3, s2, s3 |
| ; GFX90A-NEXT: s_sub_i32 s2, s3, s4 |
| ; GFX90A-NEXT: s_cmp_ge_u32 s3, s4 |
| ; GFX90A-NEXT: s_cselect_b32 s2, s2, s3 |
| ; GFX90A-NEXT: v_mov_b32_e32 v1, s2 |
| ; GFX90A-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX90A-NEXT: s_endpgm |
| %trunc_i16 = trunc i32 %input to i16 |
| %dividend = sext i16 %trunc_i16 to i32 |
| %divisor = or i32 %dividend, 1 |
| %result = urem i32 %dividend, %divisor |
| store i32 %result, ptr addrspace(1) %out, align 4 |
| ret void |
| } |
| |
| define amdgpu_kernel void @urem_i32_and_i24_fast_path(ptr addrspace(1) %out, i32 %input) { |
| ; GFX950-LABEL: urem_i32_and_i24_fast_path: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_load_dword s0, s[4:5], 0x2c |
| ; GFX950-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX950-NEXT: s_load_dword s3, s[4:5], 0x2c |
| ; GFX950-NEXT: s_mov_b32 s2, 0xffffff |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_and_b32 s3, s3, s2 |
| ; GFX950-NEXT: s_mov_b32 s5, 1 |
| ; GFX950-NEXT: s_or_b32 s4, s3, s5 |
| ; GFX950-NEXT: v_cvt_f32_u32_e64 v2, s3 |
| ; GFX950-NEXT: v_cvt_f32_u32_e64 v3, s4 |
| ; GFX950-NEXT: v_rcp_f32_e64 v1, v3 |
| ; GFX950-NEXT: s_nop 0 |
| ; GFX950-NEXT: v_mul_f32_e64 v1, v2, v1 |
| ; GFX950-NEXT: v_trunc_f32_e64 v1, v1 |
| ; GFX950-NEXT: v_fma_f32 v2, -v1, v3, v2 |
| ; GFX950-NEXT: v_cmp_ge_f32_e64 s[8:9], |v2|, |v3| |
| ; GFX950-NEXT: s_mov_b32 s6, 0 |
| ; GFX950-NEXT: s_and_b64 s[8:9], s[8:9], exec |
| ; GFX950-NEXT: s_cselect_b32 s5, s5, s6 |
| ; GFX950-NEXT: v_cvt_u32_f32_e64 v1, v1 |
| ; GFX950-NEXT: v_add_u32_e64 v1, v1, s5 |
| ; GFX950-NEXT: v_mul_lo_u32 v1, v1, s4 |
| ; GFX950-NEXT: v_sub_u32_e64 v1, s3, v1 |
| ; GFX950-NEXT: v_and_b32_e64 v1, v1, s2 |
| ; GFX950-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX950-NEXT: s_endpgm |
| ; |
| ; GFX90A-LABEL: urem_i32_and_i24_fast_path: |
| ; GFX90A: ; %bb.0: |
| ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_load_dword s0, s[4:5], 0x2c |
| ; GFX90A-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX90A-NEXT: s_load_dword s3, s[4:5], 0x2c |
| ; GFX90A-NEXT: s_mov_b32 s2, 0xffffff |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_and_b32 s3, s3, s2 |
| ; GFX90A-NEXT: s_mov_b32 s5, 1 |
| ; GFX90A-NEXT: s_or_b32 s4, s3, s5 |
| ; GFX90A-NEXT: v_cvt_f32_u32_e64 v2, s3 |
| ; GFX90A-NEXT: v_cvt_f32_u32_e64 v3, s4 |
| ; GFX90A-NEXT: v_rcp_f32_e64 v1, v3 |
| ; GFX90A-NEXT: v_mul_f32_e64 v1, v2, v1 |
| ; GFX90A-NEXT: v_trunc_f32_e64 v1, v1 |
| ; GFX90A-NEXT: v_mad_f32 v2, -v1, v3, v2 |
| ; GFX90A-NEXT: v_cmp_ge_f32_e64 s[8:9], |v2|, |v3| |
| ; GFX90A-NEXT: s_mov_b32 s6, 0 |
| ; GFX90A-NEXT: s_and_b64 s[8:9], s[8:9], exec |
| ; GFX90A-NEXT: s_cselect_b32 s5, s5, s6 |
| ; GFX90A-NEXT: v_cvt_u32_f32_e64 v1, v1 |
| ; GFX90A-NEXT: v_add_u32_e64 v1, v1, s5 |
| ; GFX90A-NEXT: v_mul_lo_u32 v1, v1, s4 |
| ; GFX90A-NEXT: v_sub_u32_e64 v1, s3, v1 |
| ; GFX90A-NEXT: v_and_b32_e64 v1, v1, s2 |
| ; GFX90A-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX90A-NEXT: s_endpgm |
| %dividend = and i32 %input, u0xffffff |
| %divisor = or i32 %dividend, 1 |
| %result = urem i32 %dividend, %divisor |
| store i32 %result, ptr addrspace(1) %out, align 4 |
| ret void |
| } |
| |
| define amdgpu_kernel void @srem_i32_i16_fast_path(ptr addrspace(1) %out, i32 %input) { |
| ; GFX950-LABEL: srem_i32_i16_fast_path: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_load_dword s0, s[4:5], 0x2c |
| ; GFX950-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX950-NEXT: s_load_dword s2, s[4:5], 0x2c |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_sext_i32_i16 s2, s2 |
| ; GFX950-NEXT: s_mov_b32 s5, 1 |
| ; GFX950-NEXT: s_or_b32 s3, s2, s5 |
| ; GFX950-NEXT: v_cvt_f32_i32_e64 v3, s3 |
| ; GFX950-NEXT: v_rcp_f32_e64 v1, v3 |
| ; GFX950-NEXT: v_cvt_f32_i32_e64 v2, s2 |
| ; GFX950-NEXT: v_mul_f32_e64 v1, v2, v1 |
| ; GFX950-NEXT: v_trunc_f32_e64 v1, v1 |
| ; GFX950-NEXT: v_fma_f32 v2, -v1, v3, v2 |
| ; GFX950-NEXT: v_cmp_ge_f32_e64 s[6:7], |v2|, |v3| |
| ; GFX950-NEXT: s_xor_b32 s4, s2, s3 |
| ; GFX950-NEXT: s_mov_b32 s8, 30 |
| ; GFX950-NEXT: s_ashr_i32 s4, s4, s8 |
| ; GFX950-NEXT: s_or_b32 s4, s4, s5 |
| ; GFX950-NEXT: s_mov_b32 s5, 0 |
| ; GFX950-NEXT: s_and_b64 s[6:7], s[6:7], exec |
| ; GFX950-NEXT: s_cselect_b32 s4, s4, s5 |
| ; GFX950-NEXT: v_cvt_i32_f32_e64 v1, v1 |
| ; GFX950-NEXT: v_add_u32_e64 v1, v1, s4 |
| ; GFX950-NEXT: v_mul_lo_u32 v1, v1, s3 |
| ; GFX950-NEXT: v_sub_u32_e64 v1, s2, v1 |
| ; GFX950-NEXT: v_bfe_i32 v1, v1, 0, 16 |
| ; GFX950-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX950-NEXT: s_endpgm |
| ; |
| ; GFX90A-LABEL: srem_i32_i16_fast_path: |
| ; GFX90A: ; %bb.0: |
| ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_load_dword s0, s[4:5], 0x2c |
| ; GFX90A-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX90A-NEXT: s_load_dword s2, s[4:5], 0x2c |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_sext_i32_i16 s2, s2 |
| ; GFX90A-NEXT: s_mov_b32 s5, 1 |
| ; GFX90A-NEXT: s_or_b32 s3, s2, s5 |
| ; GFX90A-NEXT: v_cvt_f32_i32_e64 v3, s3 |
| ; GFX90A-NEXT: v_rcp_f32_e64 v1, v3 |
| ; GFX90A-NEXT: v_cvt_f32_i32_e64 v2, s2 |
| ; GFX90A-NEXT: v_mul_f32_e64 v1, v2, v1 |
| ; GFX90A-NEXT: v_trunc_f32_e64 v1, v1 |
| ; GFX90A-NEXT: v_mad_f32 v2, -v1, v3, v2 |
| ; GFX90A-NEXT: v_cmp_ge_f32_e64 s[6:7], |v2|, |v3| |
| ; GFX90A-NEXT: s_xor_b32 s4, s2, s3 |
| ; GFX90A-NEXT: s_mov_b32 s8, 30 |
| ; GFX90A-NEXT: s_ashr_i32 s4, s4, s8 |
| ; GFX90A-NEXT: s_or_b32 s4, s4, s5 |
| ; GFX90A-NEXT: s_mov_b32 s5, 0 |
| ; GFX90A-NEXT: s_and_b64 s[6:7], s[6:7], exec |
| ; GFX90A-NEXT: s_cselect_b32 s4, s4, s5 |
| ; GFX90A-NEXT: v_cvt_i32_f32_e64 v1, v1 |
| ; GFX90A-NEXT: v_add_u32_e64 v1, v1, s4 |
| ; GFX90A-NEXT: v_mul_lo_u32 v1, v1, s3 |
| ; GFX90A-NEXT: v_sub_u32_e64 v1, s2, v1 |
| ; GFX90A-NEXT: v_bfe_i32 v1, v1, 0, 16 |
| ; GFX90A-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX90A-NEXT: s_endpgm |
| %trunc_i16 = trunc i32 %input to i16 |
| %dividend = sext i16 %trunc_i16 to i32 |
| %divisor = or i32 %dividend, 1 |
| %result = srem i32 %dividend, %divisor |
| store i32 %result, ptr addrspace(1) %out, align 4 |
| ret void |
| } |
| |
| define amdgpu_kernel void @srem_i32_i16_no_fast_path(ptr addrspace(1) %out, i32 %input) { |
| ; GFX950-LABEL: srem_i32_i16_no_fast_path: |
| ; GFX950: ; %bb.0: |
| ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_load_dword s0, s[4:5], 0x2c |
| ; GFX950-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX950-NEXT: s_nop 0 |
| ; GFX950-NEXT: s_load_dword s4, s[4:5], 0x2c |
| ; GFX950-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX950-NEXT: s_mov_b32 s2, s4 |
| ; GFX950-NEXT: s_sext_i32_i16 s2, s2 |
| ; GFX950-NEXT: s_mov_b32 s6, 0 |
| ; GFX950-NEXT: s_cmp_lt_i32 s4, s6 |
| ; GFX950-NEXT: s_mov_b32 s3, -1 |
| ; GFX950-NEXT: s_cselect_b32 s5, s3, s6 |
| ; GFX950-NEXT: s_add_i32 s4, s4, s5 |
| ; GFX950-NEXT: s_xor_b32 s5, s4, s5 |
| ; GFX950-NEXT: s_sub_i32 s4, s6, s5 |
| ; GFX950-NEXT: v_cvt_f32_u32_e32 v1, s5 |
| ; GFX950-NEXT: v_rcp_iflag_f32_e32 v1, v1 |
| ; GFX950-NEXT: s_nop 0 |
| ; GFX950-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 |
| ; GFX950-NEXT: v_cvt_u32_f32_e32 v1, v1 |
| ; GFX950-NEXT: s_nop 0 |
| ; GFX950-NEXT: v_readfirstlane_b32 s7, v1 |
| ; GFX950-NEXT: s_mul_i32 s7, s4, s7 |
| ; GFX950-NEXT: v_readfirstlane_b32 s4, v1 |
| ; GFX950-NEXT: s_mul_hi_u32 s7, s4, s7 |
| ; GFX950-NEXT: v_readfirstlane_b32 s4, v1 |
| ; GFX950-NEXT: s_add_i32 s4, s4, s7 |
| ; GFX950-NEXT: s_cmp_lt_i32 s2, s6 |
| ; GFX950-NEXT: s_cselect_b32 s3, s3, s6 |
| ; GFX950-NEXT: s_add_i32 s2, s2, s3 |
| ; GFX950-NEXT: s_xor_b32 s2, s2, s3 |
| ; GFX950-NEXT: s_mul_hi_u32 s4, s2, s4 |
| ; GFX950-NEXT: s_mul_i32 s4, s4, s5 |
| ; GFX950-NEXT: s_sub_i32 s4, s2, s4 |
| ; GFX950-NEXT: s_sub_i32 s2, s4, s5 |
| ; GFX950-NEXT: s_cmp_ge_u32 s4, s5 |
| ; GFX950-NEXT: s_cselect_b32 s4, s2, s4 |
| ; GFX950-NEXT: s_sub_i32 s2, s4, s5 |
| ; GFX950-NEXT: s_cmp_ge_u32 s4, s5 |
| ; GFX950-NEXT: s_cselect_b32 s2, s2, s4 |
| ; GFX950-NEXT: s_xor_b32 s2, s2, s3 |
| ; GFX950-NEXT: s_sub_i32 s2, s2, s3 |
| ; GFX950-NEXT: v_mov_b32_e32 v1, s2 |
| ; GFX950-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX950-NEXT: s_endpgm |
| ; |
| ; GFX90A-LABEL: srem_i32_i16_no_fast_path: |
| ; GFX90A: ; %bb.0: |
| ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_load_dword s0, s[4:5], 0x2c |
| ; GFX90A-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 |
| ; GFX90A-NEXT: s_nop 0 |
| ; GFX90A-NEXT: s_load_dword s4, s[4:5], 0x2c |
| ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX90A-NEXT: s_mov_b32 s2, s4 |
| ; GFX90A-NEXT: s_sext_i32_i16 s2, s2 |
| ; GFX90A-NEXT: s_mov_b32 s6, 0 |
| ; GFX90A-NEXT: s_cmp_lt_i32 s4, s6 |
| ; GFX90A-NEXT: s_mov_b32 s3, -1 |
| ; GFX90A-NEXT: s_cselect_b32 s5, s3, s6 |
| ; GFX90A-NEXT: s_add_i32 s4, s4, s5 |
| ; GFX90A-NEXT: s_xor_b32 s5, s4, s5 |
| ; GFX90A-NEXT: s_sub_i32 s4, s6, s5 |
| ; GFX90A-NEXT: v_cvt_f32_u32_e32 v1, s5 |
| ; GFX90A-NEXT: v_rcp_iflag_f32_e32 v1, v1 |
| ; GFX90A-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 |
| ; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1 |
| ; GFX90A-NEXT: v_readfirstlane_b32 s7, v1 |
| ; GFX90A-NEXT: s_mul_i32 s7, s4, s7 |
| ; GFX90A-NEXT: v_readfirstlane_b32 s4, v1 |
| ; GFX90A-NEXT: s_mul_hi_u32 s7, s4, s7 |
| ; GFX90A-NEXT: v_readfirstlane_b32 s4, v1 |
| ; GFX90A-NEXT: s_add_i32 s4, s4, s7 |
| ; GFX90A-NEXT: s_cmp_lt_i32 s2, s6 |
| ; GFX90A-NEXT: s_cselect_b32 s3, s3, s6 |
| ; GFX90A-NEXT: s_add_i32 s2, s2, s3 |
| ; GFX90A-NEXT: s_xor_b32 s2, s2, s3 |
| ; GFX90A-NEXT: s_mul_hi_u32 s4, s2, s4 |
| ; GFX90A-NEXT: s_mul_i32 s4, s4, s5 |
| ; GFX90A-NEXT: s_sub_i32 s4, s2, s4 |
| ; GFX90A-NEXT: s_sub_i32 s2, s4, s5 |
| ; GFX90A-NEXT: s_cmp_ge_u32 s4, s5 |
| ; GFX90A-NEXT: s_cselect_b32 s4, s2, s4 |
| ; GFX90A-NEXT: s_sub_i32 s2, s4, s5 |
| ; GFX90A-NEXT: s_cmp_ge_u32 s4, s5 |
| ; GFX90A-NEXT: s_cselect_b32 s2, s2, s4 |
| ; GFX90A-NEXT: s_xor_b32 s2, s2, s3 |
| ; GFX90A-NEXT: s_sub_i32 s2, s2, s3 |
| ; GFX90A-NEXT: v_mov_b32_e32 v1, s2 |
| ; GFX90A-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX90A-NEXT: s_endpgm |
| %trunc_i16 = trunc i32 %input to i16 |
| %dividend = sext i16 %trunc_i16 to i32 |
| %result = srem i32 %dividend, %input |
| store i32 %result, ptr addrspace(1) %out, align 4 |
| ret void |
| } |
