test/CodeGen/AMDGPU/d16-write-vgpr32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s

; Wait 0 bewteen load_d16_hi16 and or(v0.l,v0.l)
define amdgpu_kernel void @d16_load_and_valu(ptr %in1, ptr %in2) {
; GFX11-LABEL: d16_load_and_valu:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
; GFX11-NEXT:    v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2
; GFX11-NEXT:    flat_load_d16_b16 v0, v[1:2]
; GFX11-NEXT:    flat_load_d16_hi_b16 v0, v[3:4]
; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_or_b16 v0.l, v0.l, 1
; GFX11-NEXT:    v_or_b16 v0.h, v0.h, 1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_add_nc_u16 v0.l, v0.l, 10
; GFX11-NEXT:    flat_store_b16 v[1:2], v0
; GFX11-NEXT:    flat_store_d16_hi_b16 v[3:4], v0
; GFX11-NEXT:    s_endpgm
;
; GFX12-LABEL: d16_load_and_valu:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
; GFX12-NEXT:    v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2
; GFX12-NEXT:    flat_load_d16_b16 v0, v[1:2]
; GFX12-NEXT:    flat_load_d16_hi_b16 v0, v[3:4]
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    v_or_b16 v0.l, v0.l, 1
; GFX12-NEXT:    v_or_b16 v0.h, v0.h, 1
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT:    v_add_nc_u16 v0.l, v0.l, 10
; GFX12-NEXT:    flat_store_b16 v[1:2], v0
; GFX12-NEXT:    flat_store_d16_hi_b16 v[3:4], v0
; GFX12-NEXT:    s_endpgm
  %i16a = load i16, ptr %in1, align 2
  %or1 = or i16 %i16a, 1
  %i16b = load i16, ptr %in2, align 2
  %add = add i16 %or1, 10
  %or2 = or i16 %i16b, 1
  store i16 %add, ptr %in1, align 2
  store i16 %or2, ptr %in2, align 2
  ret void
}

; No wait bewteen load_d16 and load_d16_hi from same order group
define amdgpu_kernel void @d16_load_same_order_group(ptr %in1, ptr %in2) {
; GFX11-LABEL: d16_load_same_order_group:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    v_dual_mov_b32 v0, 16 :: v_dual_mov_b32 v1, 0
; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT:    flat_load_b32 v0, v[0:1]
; GFX11-NEXT:    v_mov_b32_e32 v1, 0
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX11-NEXT:    s_waitcnt vmcnt(0)
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
; GFX11-NEXT:    v_add_co_u32 v4, vcc_lo, s2, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT:    v_add_co_ci_u32_e64 v5, null, s3, v1, vcc_lo
; GFX11-NEXT:    flat_load_d16_b16 v0, v[2:3]
; GFX11-NEXT:    flat_load_d16_hi_b16 v0, v[4:5]
; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_or_b16 v0.l, v0.l, v0.h
; GFX11-NEXT:    flat_store_b16 v[2:3], v0
; GFX11-NEXT:    s_endpgm
;
; GFX12-LABEL: d16_load_same_order_group:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    v_dual_mov_b32 v0, 16 :: v_dual_mov_b32 v1, 0
; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-NEXT:    flat_load_b32 v0, v[0:1]
; GFX12-NEXT:    v_mov_b32_e32 v1, 0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT:    v_lshlrev_b64_e32 v[0:1], 1, v[0:1]
; GFX12-NEXT:    v_add_co_u32 v4, vcc_lo, s2, v0
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT:    v_add_co_ci_u32_e64 v5, null, s3, v1, vcc_lo
; GFX12-NEXT:    flat_load_d16_b16 v0, v[2:3]
; GFX12-NEXT:    flat_load_d16_hi_b16 v0, v[4:5]
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    v_or_b16 v0.l, v0.l, v0.h
; GFX12-NEXT:    flat_store_b16 v[2:3], v0
; GFX12-NEXT:    s_endpgm
  %i32 = load i32, ptr inttoptr (i64 16 to ptr), align 4
  %i16a = load i16, ptr %in1, align 2
  %zext = zext i32 %i32 to i64
  %gep = getelementptr i16, ptr %in2, i64 %zext
  %i16b = load i16, ptr %gep, align 2
  %or = or i16 %i16a, %i16b
  store i16 %or, ptr %in1, align 2
  ret void
}

; Wait bewteen load_d16 and load_d16_hi from two order group
define amdgpu_kernel void @d16_two_order_group(ptr addrspace(3) %in1, ptr %in2) {
; GFX11-LABEL: d16_two_order_group:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x2c
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
; GFX11-NEXT:    s_load_b32 s0, s[4:5], 0x24
; GFX11-NEXT:    flat_load_d16_b16 v0, v[1:2]
; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-NEXT:    v_mov_b32_e32 v3, s0
; GFX11-NEXT:    ds_load_u16_d16_hi v0, v3
; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_or_b16 v0.l, v0.h, v0.l
; GFX11-NEXT:    flat_store_b16 v[1:2], v0
; GFX11-NEXT:    s_endpgm
;
; GFX12-LABEL: d16_two_order_group:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x2c
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
; GFX12-NEXT:    s_load_b32 s0, s[4:5], 0x24
; GFX12-NEXT:    flat_load_d16_b16 v0, v[1:2]
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_mov_b32_e32 v3, s0
; GFX12-NEXT:    ds_load_u16_d16_hi v0, v3
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    v_or_b16 v0.l, v0.h, v0.l
; GFX12-NEXT:    flat_store_b16 v[1:2], v0
; GFX12-NEXT:    s_endpgm
  %i16a = load i16, ptr addrspace(3) %in1, align 2
  %i16b = load i16, ptr %in2, align 2
  %or = or i16 %i16a, %i16b
  store i16 %or, ptr %in2, align 2
  ret void
}