test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-minmax-uminmax.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s

# Test G_ATOMICRMW_MIN, G_ATOMICRMW_MAX, G_ATOMICRMW_UMIN, G_ATOMICRMW_UMAX
# register bank selection and legalization for flat, global, and local address spaces.

---
name: atomicrmw_min_flat_s32_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-LABEL: name: atomicrmw_min_flat_s32_vv
    ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
    ; CHECK-NEXT: [[ATOMICRMW_MIN:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_MIN [[COPY]](p0), [[COPY1]] :: (load store seq_cst (s32))
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ATOMICRMW_MIN]], [[ATOMICRMW_MIN]]
    %0:_(p0) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(s32) = G_ATOMICRMW_MIN %0, %1 :: (load store seq_cst (s32), addrspace 0)
    %3:_(s32) = G_AND %2, %2
...

---
name: atomicrmw_min_global_s32_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-LABEL: name: atomicrmw_min_global_s32_vv
    ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
    ; CHECK-NEXT: [[ATOMICRMW_MIN:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_MIN [[COPY]](p1), [[COPY1]] :: (load store seq_cst (s32), addrspace 1)
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ATOMICRMW_MIN]], [[ATOMICRMW_MIN]]
    %0:_(p1) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(s32) = G_ATOMICRMW_MIN %0, %1 :: (load store seq_cst (s32), addrspace 1)
    %3:_(s32) = G_AND %2, %2
...

---
name: atomicrmw_min_local_s32_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; CHECK-LABEL: name: atomicrmw_min_local_s32_vv
    ; CHECK: liveins: $vgpr0, $vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
    ; CHECK-NEXT: [[ATOMICRMW_MIN:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_MIN [[COPY]](p3), [[COPY1]] :: (load store seq_cst (s32), addrspace 3)
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ATOMICRMW_MIN]], [[ATOMICRMW_MIN]]
    %0:_(p3) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s32) = G_ATOMICRMW_MIN %0, %1 :: (load store seq_cst (s32), addrspace 3)
    %3:_(s32) = G_AND %2, %2
...

---
name: atomicrmw_max_flat_s32_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-LABEL: name: atomicrmw_max_flat_s32_vv
    ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
    ; CHECK-NEXT: [[ATOMICRMW_MAX:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_MAX [[COPY]](p0), [[COPY1]] :: (load store seq_cst (s32))
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ATOMICRMW_MAX]], [[ATOMICRMW_MAX]]
    %0:_(p0) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(s32) = G_ATOMICRMW_MAX %0, %1 :: (load store seq_cst (s32), addrspace 0)
    %3:_(s32) = G_AND %2, %2
...

---
name: atomicrmw_max_global_s32_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-LABEL: name: atomicrmw_max_global_s32_vv
    ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
    ; CHECK-NEXT: [[ATOMICRMW_MAX:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_MAX [[COPY]](p1), [[COPY1]] :: (load store seq_cst (s32), addrspace 1)
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ATOMICRMW_MAX]], [[ATOMICRMW_MAX]]
    %0:_(p1) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(s32) = G_ATOMICRMW_MAX %0, %1 :: (load store seq_cst (s32), addrspace 1)
    %3:_(s32) = G_AND %2, %2
...

---
name: atomicrmw_max_local_s32_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; CHECK-LABEL: name: atomicrmw_max_local_s32_vv
    ; CHECK: liveins: $vgpr0, $vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
    ; CHECK-NEXT: [[ATOMICRMW_MAX:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_MAX [[COPY]](p3), [[COPY1]] :: (load store seq_cst (s32), addrspace 3)
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ATOMICRMW_MAX]], [[ATOMICRMW_MAX]]
    %0:_(p3) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s32) = G_ATOMICRMW_MAX %0, %1 :: (load store seq_cst (s32), addrspace 3)
    %3:_(s32) = G_AND %2, %2
...

---
name: atomicrmw_umin_flat_s32_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-LABEL: name: atomicrmw_umin_flat_s32_vv
    ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
    ; CHECK-NEXT: [[ATOMICRMW_UMIN:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_UMIN [[COPY]](p0), [[COPY1]] :: (load store seq_cst (s32))
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ATOMICRMW_UMIN]], [[ATOMICRMW_UMIN]]
    %0:_(p0) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(s32) = G_ATOMICRMW_UMIN %0, %1 :: (load store seq_cst (s32), addrspace 0)
    %3:_(s32) = G_AND %2, %2
...

---
name: atomicrmw_umin_global_s32_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-LABEL: name: atomicrmw_umin_global_s32_vv
    ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
    ; CHECK-NEXT: [[ATOMICRMW_UMIN:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_UMIN [[COPY]](p1), [[COPY1]] :: (load store seq_cst (s32), addrspace 1)
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ATOMICRMW_UMIN]], [[ATOMICRMW_UMIN]]
    %0:_(p1) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(s32) = G_ATOMICRMW_UMIN %0, %1 :: (load store seq_cst (s32), addrspace 1)
    %3:_(s32) = G_AND %2, %2
...

---
name: atomicrmw_umin_local_s32_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; CHECK-LABEL: name: atomicrmw_umin_local_s32_vv
    ; CHECK: liveins: $vgpr0, $vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
    ; CHECK-NEXT: [[ATOMICRMW_UMIN:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_UMIN [[COPY]](p3), [[COPY1]] :: (load store seq_cst (s32), addrspace 3)
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ATOMICRMW_UMIN]], [[ATOMICRMW_UMIN]]
    %0:_(p3) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s32) = G_ATOMICRMW_UMIN %0, %1 :: (load store seq_cst (s32), addrspace 3)
    %3:_(s32) = G_AND %2, %2
...

---
name: atomicrmw_umax_flat_s32_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-LABEL: name: atomicrmw_umax_flat_s32_vv
    ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
    ; CHECK-NEXT: [[ATOMICRMW_UMAX:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_UMAX [[COPY]](p0), [[COPY1]] :: (load store seq_cst (s32))
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ATOMICRMW_UMAX]], [[ATOMICRMW_UMAX]]
    %0:_(p0) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(s32) = G_ATOMICRMW_UMAX %0, %1 :: (load store seq_cst (s32), addrspace 0)
    %3:_(s32) = G_AND %2, %2
...

---
name: atomicrmw_umax_global_s32_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-LABEL: name: atomicrmw_umax_global_s32_vv
    ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
    ; CHECK-NEXT: [[ATOMICRMW_UMAX:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_UMAX [[COPY]](p1), [[COPY1]] :: (load store seq_cst (s32), addrspace 1)
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ATOMICRMW_UMAX]], [[ATOMICRMW_UMAX]]
    %0:_(p1) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(s32) = G_ATOMICRMW_UMAX %0, %1 :: (load store seq_cst (s32), addrspace 1)
    %3:_(s32) = G_AND %2, %2
...

---
name: atomicrmw_umax_local_s32_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; CHECK-LABEL: name: atomicrmw_umax_local_s32_vv
    ; CHECK: liveins: $vgpr0, $vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
    ; CHECK-NEXT: [[ATOMICRMW_UMAX:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_UMAX [[COPY]](p3), [[COPY1]] :: (load store seq_cst (s32), addrspace 3)
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ATOMICRMW_UMAX]], [[ATOMICRMW_UMAX]]
    %0:_(p3) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s32) = G_ATOMICRMW_UMAX %0, %1 :: (load store seq_cst (s32), addrspace 3)
    %3:_(s32) = G_AND %2, %2
...