test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-wave-address.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1031 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1031 -mattr=+wavefrontsize64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE64 %s

---
name: wave_address_s
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  stackPtrOffsetReg: $sgpr32
body: |
  bb.0:
    ; WAVE32-LABEL: name: wave_address_s
    ; WAVE32: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc
    ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_LSHR_B32_]]
    ;
    ; WAVE64-LABEL: name: wave_address_s
    ; WAVE64: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc
    ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_LSHR_B32_]]
    %0:sgpr(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
    S_ENDPGM 0, implicit %0
...

---
name: wave_address_v
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  stackPtrOffsetReg: $sgpr32
body: |
  bb.0:
    ; WAVE32-LABEL: name: wave_address_v
    ; WAVE32: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec
    ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]
    ;
    ; WAVE64-LABEL: name: wave_address_v
    ; WAVE64: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec
    ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]
    %0:vgpr(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
    S_ENDPGM 0, implicit %0
...