test/CodeGen/AMDGPU/GlobalISel/combine-or-s64-s32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=amdgpu-prelegalizer-combiner %s -o - | FileCheck %s

---
name: test_combine_or_s64_s32
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0_sgpr1, $sgpr2
    ; CHECK-LABEL: name: test_combine_or_s64_s32
    ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[COPY1]]
    ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[UV1]](s32)
    ; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[MV]](s64)
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0_sgpr1
    %0:_(s64) = COPY $sgpr0_sgpr1
    %1:_(s32) = COPY $sgpr2
    %2:_(s64) = G_ZEXT %1(s32)
    %3:_(s64) = G_OR %0, %2
    $sgpr0_sgpr1 = COPY %3(s64)
    SI_RETURN_TO_EPILOG implicit $sgpr0_sgpr1
...
---
name: test_combine_or_s64_s32_rhs
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0_sgpr1, $sgpr2
    ; CHECK-LABEL: name: test_combine_or_s64_s32_rhs
    ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[COPY1]]
    ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[UV1]](s32)
    ; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[MV]](s64)
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0_sgpr1
    %0:_(s64) = COPY $sgpr0_sgpr1
    %1:_(s32) = COPY $sgpr2
    %2:_(s64) = G_ZEXT %1(s32)
    %3:_(s64) = G_OR %2, %0
    $sgpr0_sgpr1 = COPY %3(s64)
    SI_RETURN_TO_EPILOG implicit $sgpr0_sgpr1
...
---
name: test_combine_or_s64_s32_merge_unmerge
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0, $sgpr1, $sgpr2
    ; CHECK-LABEL: name: test_combine_or_s64_s32_merge_unmerge
    ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr2
    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY2]]
    ; CHECK-NEXT: $sgpr0 = COPY [[OR]](s32)
    ; CHECK-NEXT: $sgpr1 = COPY [[COPY1]](s32)
    ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = COPY $sgpr1
    %2:_(s32) = COPY $sgpr2
    %3:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)
    %4:_(s64) = G_ZEXT %2(s32)
    %5:_(s64) = G_OR %3, %4
    %6:_(s32), %7:_(s32) = G_UNMERGE_VALUES %5(s64)
    $sgpr0 = COPY %6(s32)
    $sgpr1 = COPY %7(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
...
---
name: negative_test_incorrect_types
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
    ; CHECK-LABEL: name: negative_test_incorrect_types
    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s128) = G_ZEXT [[COPY1]](s64)
    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s128) = G_OR [[COPY]], [[ZEXT]]
    ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[OR]](s128)
    %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    %1:_(s64) = COPY $vgpr4_vgpr5
    %2:_(s128) = G_ZEXT %1
    %3:_(s128) = G_OR %0, %2
    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
...