test/CodeGen/AArch64/volatile-reg-writeback.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel < %s | FileCheck %s

; Make sure postinc/preinc addressing mode is not used for volatile accesses,
; see https://github.com/llvm/llvm-project/issues/173014.

define ptr @volatile_store_postinc(ptr %p) {
; CHECK-LABEL: volatile_store_postinc:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov x8, x0
; CHECK-NEXT:    add x0, x0, #4
; CHECK-NEXT:    str wzr, [x8]
; CHECK-NEXT:    ret
  store volatile i32 0, ptr %p
  %gep = getelementptr i8, ptr %p, i64 4
  ret ptr %gep
}

define ptr @volatile_load_postinc(ptr %p) {
; CHECK-LABEL: volatile_load_postinc:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr wzr, [x0]
; CHECK-NEXT:    add x0, x0, #4
; CHECK-NEXT:    ret
  load volatile i32, ptr %p
  %gep = getelementptr i8, ptr %p, i64 4
  ret ptr %gep
}

define ptr @volatile_store_preinc(ptr %p) {
; CHECK-LABEL: volatile_store_preinc:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov x8, x0
; CHECK-NEXT:    add x0, x0, #4
; CHECK-NEXT:    str wzr, [x8, #4]
; CHECK-NEXT:    ret
  %gep = getelementptr i8, ptr %p, i64 4
  store volatile i32 0, ptr %gep
  ret ptr %gep
}

define ptr @volatile_load_preinc(ptr %p) {
; CHECK-LABEL: volatile_load_preinc:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr wzr, [x0, #4]
; CHECK-NEXT:    add x0, x0, #4
; CHECK-NEXT:    ret
  %gep = getelementptr i8, ptr %p, i64 4
  load volatile i32, ptr %gep
  ret ptr %gep
}