test/CodeGen/AArch64/shr-exact-demanded-bits.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s | FileCheck %s
target triple = "aarch64-linux"

define <2 x i32> @f(i8  %0, i8  %1) {
; CHECK-LABEL: f:
; CHECK:       // %bb.0:
; CHECK-NEXT:    movi v0.2d, #0000000000000000
; CHECK-NEXT:    mov v0.b[3], w0
; CHECK-NEXT:    mov v0.b[7], w1
; CHECK-NEXT:    sshr v0.2s, v0.2s, #24
; CHECK-NEXT:    ret
  %3 = insertelement <2 x i8> poison, i8 %0, i64 0
  %4 = insertelement <2 x i8> %3, i8 %1, i64 1
  %5 = shufflevector <2 x i8> %4, <2 x i8> <i8 0, i8 poison>, <8 x i32> <i32 2, i32 2, i32 2, i32 0, i32 2, i32 2, i32 2, i32 1>
  %6 = bitcast <8 x i8> %5 to <2 x i32>
  %7 = ashr exact <2 x i32> %6, <i32 24, i32 24>
  ret <2 x i32> %7
}

define <2 x i32> @g(i8  %0, i8  %1) {
; CHECK-LABEL: g:
; CHECK:       // %bb.0:
; CHECK-NEXT:    movi v0.2d, #0000000000000000
; CHECK-NEXT:    mov v0.b[3], w0
; CHECK-NEXT:    mov v0.b[7], w1
; CHECK-NEXT:    ushr v0.2s, v0.2s, #24
; CHECK-NEXT:    ret
  %3 = insertelement <2 x i8> poison, i8 %0, i64 0
  %4 = insertelement <2 x i8> %3, i8 %1, i64 1
  %5 = shufflevector <2 x i8> %4, <2 x i8> <i8 0, i8 poison>, <8 x i32> <i32 2, i32 2, i32 2, i32 0, i32 2, i32 2, i32 2, i32 1>
  %6 = bitcast <8 x i8> %5 to <2 x i32>
  %7 = lshr exact <2 x i32> %6, <i32 24, i32 24>
  ret <2 x i32> %7
}