test/CodeGen/AArch64/select_of_select.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s

define <2 x i8> @src_a(<2 x i1> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d) {
; CHECK-LABEL: src_a:
; CHECK:       // %bb.0:
; CHECK-NEXT:    shl v0.2s, v0.2s, #31
; CHECK-NEXT:    cmlt v0.2s, v0.2s, #0
; CHECK-NEXT:    bif v1.8b, v2.8b, v0.8b
; CHECK-NEXT:    bsl v0.8b, v1.8b, v3.8b
; CHECK-NEXT:    ret
  %s = select <2 x i1> %a, <2 x i8> %b, <2 x i8> %c
  %t = select <2 x i1> %a, <2 x i8> %s, <2 x i8> %d
  ret <2 x i8> %t
}

define <2 x i8> @tgt_a(<2 x i1> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d) {
; CHECK-LABEL: tgt_a:
; CHECK:       // %bb.0:
; CHECK-NEXT:    shl v0.2s, v0.2s, #31
; CHECK-NEXT:    cmlt v0.2s, v0.2s, #0
; CHECK-NEXT:    bsl v0.8b, v1.8b, v3.8b
; CHECK-NEXT:    ret
  %t = select <2 x i1> %a, <2 x i8> %b, <2 x i8> %d
  ret <2 x i8> %t
}


define <2 x i8> @src_b(<2 x i1> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d) {
; CHECK-LABEL: src_b:
; CHECK:       // %bb.0:
; CHECK-NEXT:    shl v0.2s, v0.2s, #31
; CHECK-NEXT:    cmlt v0.2s, v0.2s, #0
; CHECK-NEXT:    bif v1.8b, v2.8b, v0.8b
; CHECK-NEXT:    bsl v0.8b, v3.8b, v1.8b
; CHECK-NEXT:    ret
  %s = select <2 x i1> %a, <2 x i8> %b, <2 x i8> %c
  %t = select <2 x i1> %a, <2 x i8> %d, <2 x i8> %s
  ret <2 x i8> %t
}

define <2 x i8> @tgt_b(<2 x i1> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d) {
; CHECK-LABEL: tgt_b:
; CHECK:       // %bb.0:
; CHECK-NEXT:    shl v0.2s, v0.2s, #31
; CHECK-NEXT:    cmlt v0.2s, v0.2s, #0
; CHECK-NEXT:    bsl v0.8b, v3.8b, v2.8b
; CHECK-NEXT:    ret
  %t = select <2 x i1> %a, <2 x i8> %d, <2 x i8> %c
  ret <2 x i8> %t
}