test/CodeGen/AArch64/powi-arm64ec.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=arm64ec-windows-msvc < %s | FileCheck -check-prefix=ARM64EC %s

declare half @llvm.powi.f16.i32(half, i32)
declare float @llvm.powi.f32.i32(float, i32)
declare double @llvm.powi.f64.i32(double, i32)

; ARM64EC-LABEL: powi_f16
; ARM64EC: fcvt  s0, h0
; ARM64EC: scvtf s1, w0
; ARM64EC: bl "#powf"
define half @powi_f16(half %x, i32 %n) nounwind {
  %ret = tail call half @llvm.powi.f16.i32(half %x, i32 %n)
  ret half %ret
}

; ARM64EC-LABEL: powi_f32
; ARM64EC: scvtf s1, w0
; ARM64EC: b "#powf"
define float @powi_f32(float %x, i32 %n) nounwind {
  %ret = tail call float @llvm.powi.f32.i32(float %x, i32 %n)
  ret float %ret
}

; ARM64EC-LABEL: powi_f64
; ARM64EC: scvtf d1, w0
; ARM64EC: b "#pow"
define double @powi_f64(double %x, i32 %n) nounwind {
  %ret = tail call double @llvm.powi.f64.i32(double %x, i32 %n)
  ret double %ret
}