test/CodeGen/AArch64/movi64_sve.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64 -mattr=+neon < %s | FileCheck %s --check-prefixes=COMMON,NEON
; RUN: llc -mtriple=aarch64 -mattr=+neon,+sve < %s | FileCheck %s --check-prefixes=COMMON,SVE

define <2 x i64> @movi_1_v2i64() {
; NEON-LABEL: movi_1_v2i64:
; NEON:       // %bb.0:
; NEON-NEXT:    mov w8, #1 // =0x1
; NEON-NEXT:    dup v0.2d, x8
; NEON-NEXT:    ret
;
; SVE-LABEL: movi_1_v2i64:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z0.d, #1 // =0x1
; SVE-NEXT:    ret
  ret <2 x i64> splat (i64 1)
}

define <2 x i64> @movi_127_v2i64() {
; NEON-LABEL: movi_127_v2i64:
; NEON:       // %bb.0:
; NEON-NEXT:    mov w8, #127 // =0x7f
; NEON-NEXT:    dup v0.2d, x8
; NEON-NEXT:    ret
;
; SVE-LABEL: movi_127_v2i64:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z0.d, #127 // =0x7f
; SVE-NEXT:    ret
  ret <2 x i64> splat (i64 127)
}

define <2 x i64> @movi_m128_v2i64() {
; NEON-LABEL: movi_m128_v2i64:
; NEON:       // %bb.0:
; NEON-NEXT:    mov x8, #-128 // =0xffffffffffffff80
; NEON-NEXT:    dup v0.2d, x8
; NEON-NEXT:    ret
;
; SVE-LABEL: movi_m128_v2i64:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z0.d, #-128 // =0xffffffffffffff80
; SVE-NEXT:    ret
  ret <2 x i64> splat (i64 -128)
}

define <2 x i64> @movi_256_v2i64() {
; NEON-LABEL: movi_256_v2i64:
; NEON:       // %bb.0:
; NEON-NEXT:    mov w8, #256 // =0x100
; NEON-NEXT:    dup v0.2d, x8
; NEON-NEXT:    ret
;
; SVE-LABEL: movi_256_v2i64:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z0.d, #256 // =0x100
; SVE-NEXT:    ret
  ret <2 x i64> splat (i64 256)
}

define <2 x i64> @movi_32512_v2i64() {
; NEON-LABEL: movi_32512_v2i64:
; NEON:       // %bb.0:
; NEON-NEXT:    mov w8, #32512 // =0x7f00
; NEON-NEXT:    dup v0.2d, x8
; NEON-NEXT:    ret
;
; SVE-LABEL: movi_32512_v2i64:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z0.d, #32512 // =0x7f00
; SVE-NEXT:    ret
  ret <2 x i64> splat (i64 32512)
}

define <2 x i64> @movi_m32768_v2i64() {
; NEON-LABEL: movi_m32768_v2i64:
; NEON:       // %bb.0:
; NEON-NEXT:    mov x8, #-32768 // =0xffffffffffff8000
; NEON-NEXT:    dup v0.2d, x8
; NEON-NEXT:    ret
;
; SVE-LABEL: movi_m32768_v2i64:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z0.d, #-32768 // =0xffffffffffff8000
; SVE-NEXT:    ret
  ret <2 x i64> splat (i64 -32768)
}

; Special cases where the destination vector does not have 64-bit elements

define <4 x i32> @movi_v4i32_1() {
; NEON-LABEL: movi_v4i32_1:
; NEON:       // %bb.0:
; NEON-NEXT:    adrp x8, .LCPI6_0
; NEON-NEXT:    ldr q0, [x8, :lo12:.LCPI6_0]
; NEON-NEXT:    ret
;
; SVE-LABEL: movi_v4i32_1:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z0.d, #127 // =0x7f
; SVE-NEXT:    ret
  ret <4 x i32> <i32 127, i32 0, i32 127, i32 0>
}

define <4 x i32> @movi_v4i32_2() {
; NEON-LABEL: movi_v4i32_2:
; NEON:       // %bb.0:
; NEON-NEXT:    adrp x8, .LCPI7_0
; NEON-NEXT:    ldr q0, [x8, :lo12:.LCPI7_0]
; NEON-NEXT:    ret
;
; SVE-LABEL: movi_v4i32_2:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z0.d, #32512 // =0x7f00
; SVE-NEXT:    ret
  ret <4 x i32> <i32 32512, i32 0, i32 32512, i32 0>
}

define <4 x i32> @movi_v4i32_4092() {
; NEON-LABEL: movi_v4i32_4092:
; NEON:       // %bb.0:
; NEON-NEXT:    mov w8, #4092 // =0xffc
; NEON-NEXT:    dup v0.4s, w8
; NEON-NEXT:    ret
;
; SVE-LABEL: movi_v4i32_4092:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z0.s, #4092 // =0xffc
; SVE-NEXT:    ret
  ret <4 x i32> splat (i32 4092)
}

define <8 x i16> @movi_v8i16_1() {
; NEON-LABEL: movi_v8i16_1:
; NEON:       // %bb.0:
; NEON-NEXT:    adrp x8, .LCPI9_0
; NEON-NEXT:    ldr q0, [x8, :lo12:.LCPI9_0]
; NEON-NEXT:    ret
;
; SVE-LABEL: movi_v8i16_1:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z0.d, #127 // =0x7f
; SVE-NEXT:    ret
  ret <8 x i16> <i16 127, i16 0, i16 0, i16 0, i16 127, i16 0, i16 0, i16 0>
}

define <8 x i16> @movi_v8i16_2() {
; NEON-LABEL: movi_v8i16_2:
; NEON:       // %bb.0:
; NEON-NEXT:    adrp x8, .LCPI10_0
; NEON-NEXT:    ldr q0, [x8, :lo12:.LCPI10_0]
; NEON-NEXT:    ret
;
; SVE-LABEL: movi_v8i16_2:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z0.d, #32512 // =0x7f00
; SVE-NEXT:    ret
  ret <8 x i16> <i16 32512, i16 0, i16 0, i16 0, i16 32512, i16 0, i16 0, i16 0>
}

define <8 x i16> @movi_v8i16_510() {
; NEON-LABEL: movi_v8i16_510:
; NEON:       // %bb.0:
; NEON-NEXT:    mov w8, #510 // =0x1fe
; NEON-NEXT:    dup v0.8h, w8
; NEON-NEXT:    ret
;
; SVE-LABEL: movi_v8i16_510:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z0.h, #510 // =0x1fe
; SVE-NEXT:    ret
  ret <8 x i16> splat (i16 510)
}

define <16 x i8> @movi_v16i8_1() {
; NEON-LABEL: movi_v16i8_1:
; NEON:       // %bb.0:
; NEON-NEXT:    adrp x8, .LCPI12_0
; NEON-NEXT:    ldr q0, [x8, :lo12:.LCPI12_0]
; NEON-NEXT:    ret
;
; SVE-LABEL: movi_v16i8_1:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z0.d, #127 // =0x7f
; SVE-NEXT:    ret
  ret <16 x i8> <i8 127, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 127, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
}

define <16 x i8> @movi_v16i8_2() {
; NEON-LABEL: movi_v16i8_2:
; NEON:       // %bb.0:
; NEON-NEXT:    adrp x8, .LCPI13_0
; NEON-NEXT:    ldr q0, [x8, :lo12:.LCPI13_0]
; NEON-NEXT:    ret
;
; SVE-LABEL: movi_v16i8_2:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z0.d, #32512 // =0x7f00
; SVE-NEXT:    ret
  ret <16 x i8> <i8 0, i8 127, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 127, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
}

; Negative cases

define <2 x i64> @movi_128_v2i64() {
; NEON-LABEL: movi_128_v2i64:
; NEON:       // %bb.0:
; NEON-NEXT:    mov w8, #128 // =0x80
; NEON-NEXT:    dup v0.2d, x8
; NEON-NEXT:    ret
;
; SVE-LABEL: movi_128_v2i64:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z0.d, #128 // =0x80
; SVE-NEXT:    ret
  ret <2 x i64> splat (i64 128)
}

define <2 x i64> @movi_m127_v2i64() {
; NEON-LABEL: movi_m127_v2i64:
; NEON:       // %bb.0:
; NEON-NEXT:    mov x8, #-129 // =0xffffffffffffff7f
; NEON-NEXT:    dup v0.2d, x8
; NEON-NEXT:    ret
;
; SVE-LABEL: movi_m127_v2i64:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z0.d, #-129 // =0xffffffffffffff7f
; SVE-NEXT:    ret
  ret <2 x i64> splat (i64 -129)
}

define <2 x i64> @movi_32513_v2i64() {
; COMMON-LABEL: movi_32513_v2i64:
; COMMON:       // %bb.0:
; COMMON-NEXT:    mov w8, #32513 // =0x7f01
; COMMON-NEXT:    dup v0.2d, x8
; COMMON-NEXT:    ret
  ret <2 x i64> splat (i64 32513)
}

define <2 x i64> @movi_m32769_v2i64() {
; NEON-LABEL: movi_m32769_v2i64:
; NEON:       // %bb.0:
; NEON-NEXT:    mov x8, #-32769 // =0xffffffffffff7fff
; NEON-NEXT:    dup v0.2d, x8
; NEON-NEXT:    ret
;
; SVE-LABEL: movi_m32769_v2i64:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z0.d, #0xffffffffffff7fff
; SVE-NEXT:    ret
  ret <2 x i64> splat (i64 -32769)
}

define <2 x i64> @movi_257_v2i64() {
; COMMON-LABEL: movi_257_v2i64:
; COMMON:       // %bb.0:
; COMMON-NEXT:    mov w8, #257 // =0x101
; COMMON-NEXT:    dup v0.2d, x8
; COMMON-NEXT:    ret
  ret <2 x i64> splat (i64 257)
}

define <4 x i32> @movi_v4i32_3() {
; NEON-LABEL: movi_v4i32_3:
; NEON:       // %bb.0:
; NEON-NEXT:    adrp x8, .LCPI19_0
; NEON-NEXT:    ldr q0, [x8, :lo12:.LCPI19_0]
; NEON-NEXT:    ret
;
; SVE-LABEL: movi_v4i32_3:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z0.d, #0xffffff80
; SVE-NEXT:    ret
  ret <4 x i32> <i32 -128, i32 0, i32 -128, i32 0>
}

define <16 x i8> @movi_v16i8_3() {
; NEON-LABEL: movi_v16i8_3:
; NEON:       // %bb.0:
; NEON-NEXT:    adrp x8, .LCPI20_0
; NEON-NEXT:    ldr q0, [x8, :lo12:.LCPI20_0]
; NEON-NEXT:    ret
;
; SVE-LABEL: movi_v16i8_3:
; SVE:       // %bb.0:
; SVE-NEXT:    mov z0.d, #0x7f0000
; SVE-NEXT:    ret
  ret <16 x i8> <i8 0, i8 0, i8 127, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 127, i8 0, i8 0, i8 0, i8 0, i8 0>
}