test/CodeGen/AArch64/load-zext-bitcast.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s

; load zero-extended i32, bitcast to f64
define double @_Z9load_u64_from_u32_testPj(ptr %n){
; CHECK-LABEL: _Z9load_u64_from_u32_testPj:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ldr s0, [x0]
; CHECK-NEXT:    ret
entry:
  %0 = load i32, ptr %n, align 4
  %conv = zext i32 %0 to i64
  %1 = bitcast i64 %conv to double
  ret double %1
}

; load zero-extended i16, bitcast to f64
define double @_Z9load_u64_from_u16_testPj(ptr %n){
; CHECK-LABEL: _Z9load_u64_from_u16_testPj:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ldr h0, [x0]
; CHECK-NEXT:    ret
entry:
  %0 = load i16, ptr %n, align 2
  %conv = zext i16 %0 to i64
  %1 = bitcast i64 %conv to double
  ret double %1
}

; load zero-extended i8, bitcast to f64
define double @_Z16load_u64_from_u8Ph(ptr %n){
; CHECK-LABEL: _Z16load_u64_from_u8Ph:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ldr b0, [x0]
; CHECK-NEXT:    ret
entry:
  %0 = load i8, ptr %n, align 1
  %conv = zext i8 %0 to i64
  %1 = bitcast i64 %conv to double
  ret double %1
}

; load zero-extended i16, bitcast to f32
define float @_Z17load_u32_from_u16Pt(ptr %n){
; CHECK-LABEL: _Z17load_u32_from_u16Pt:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ldr h0, [x0]
; CHECK-NEXT:    ret
entry:
  %0 = load i16, ptr %n, align 2
  %conv = zext i16 %0 to i32
  %1 = bitcast i32 %conv to float
  ret float %1
}

; load zero-extended i8, bitcast to f32
define float @_Z16load_u32_from_u8Ph(ptr %n){
; CHECK-LABEL: _Z16load_u32_from_u8Ph:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ldr b0, [x0]
; CHECK-NEXT:    ret
entry:
  %0 = load i8, ptr %n, align 1
  %conv = zext i8 %0 to i32
  %1 = bitcast i32 %conv to float
  ret float %1
}

; load zero-extended i8, bitcast to f16
define half @_Z16load_u16_from_u8Ph(ptr %n){
; CHECK-LABEL: _Z16load_u16_from_u8Ph:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ldr b0, [x0]
; CHECK-NEXT:    // kill: def $h0 killed $h0 killed $s0
; CHECK-NEXT:    ret
entry:
  %0 = load i8, ptr %n, align 1
  %conv = zext i8 %0 to i16
  %1 = bitcast i16 %conv to half
  ret half %1
}