test/CodeGen/AArch64/aarch64-condopt-nzcvdef.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=aarch64-linux-gnu -run-pass=aarch64-condopt -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=aarch64-linux-gnu -passes=aarch64-condopt %s -o - | FileCheck %s

---
# Negative test: cross-block compares with different physical registers should
# NOT be optimised. bb.0 compares $w0, bb.1 compares $w1.
name:            cross_block_different_regs
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: cross_block_different_regs
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT:   liveins: $w0, $d0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:fpr64 = COPY $d0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32common = COPY $w0
  ; CHECK-NEXT:   [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY1]], 11, 0, implicit-def $nzcv
  ; CHECK-NEXT:   [[FJCVTZS:%[0-9]+]]:gpr32 = FJCVTZS [[COPY]], implicit-def $nzcv, implicit $fpcr
  ; CHECK-NEXT:   Bcc 11, %bb.1, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
  ; CHECK-NEXT:   liveins: $d0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[COPY1]], 10, 0, implicit-def $nzcv
  ; CHECK-NEXT:   Bcc 11, %bb.3, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   $w0 = MOVi32imm 0
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   $w0 = MOVi32imm 1
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    liveins: $w0, $d0
    successors: %bb.1, %bb.2

    %2:fpr64 = COPY $d0
    %0:gpr32common = COPY $w0
    %1:gpr32 = SUBSWri %0, 11, 0, implicit-def $nzcv
    %4:gpr32 = FJCVTZS %2, implicit-def $nzcv, implicit $fpcr
    Bcc 11, %bb.1, implicit $nzcv
    B %bb.2

  bb.1:
    liveins: $d0
    successors: %bb.2, %bb.3

    %3:gpr32 = SUBSWri %0, 10, 0, implicit-def $nzcv
    Bcc 11, %bb.3, implicit $nzcv
    B %bb.2

  bb.2:
    $w0 = MOVi32imm 0
    RET_ReallyLR implicit $w0

  bb.3:
    $w0 = MOVi32imm 1
    RET_ReallyLR implicit $w0
...