test/Transforms/VectorCombine/X86/fold-reduction-zero-test.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -mtriple=x86_64-- -mcpu=x86-64    -passes=vector-combine -S %s | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v2 -passes=vector-combine -S %s | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v3 -passes=vector-combine -S %s | FileCheck %s --check-prefixes=CHECK,AVX2
; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v4 -passes=vector-combine -S %s | FileCheck %s --check-prefixes=CHECK,AVX512

declare i8 @llvm.vector.reduce.or.v16i8(<16 x i8>)
declare i8 @llvm.vector.reduce.umax.v16i8(<16 x i8>)

define i1 @or_nonzero(<16 x i8> %x) {
; SSE-LABEL: define i1 @or_nonzero(
; SSE-SAME: <16 x i8> [[X:%.*]]) #[[ATTR1:[0-9]+]] {
; SSE-NEXT:    [[TMP1:%.*]] = icmp ne <16 x i8> [[X]], zeroinitializer
; SSE-NEXT:    [[CMP:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP1]])
; SSE-NEXT:    ret i1 [[CMP]]
;
; AVX2-LABEL: define i1 @or_nonzero(
; AVX2-SAME: <16 x i8> [[X:%.*]]) #[[ATTR1:[0-9]+]] {
; AVX2-NEXT:    [[TMP1:%.*]] = icmp ne <16 x i8> [[X]], zeroinitializer
; AVX2-NEXT:    [[CMP:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP1]])
; AVX2-NEXT:    ret i1 [[CMP]]
;
; AVX512-LABEL: define i1 @or_nonzero(
; AVX512-SAME: <16 x i8> [[X:%.*]]) #[[ATTR1:[0-9]+]] {
; AVX512-NEXT:    [[REDUCTION:%.*]] = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> [[X]])
; AVX512-NEXT:    [[CMP:%.*]] = icmp ne i8 [[REDUCTION]], 0
; AVX512-NEXT:    ret i1 [[CMP]]
;
  %reduction = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> %x)
  %cmp = icmp ne i8 %reduction, 0
  ret i1 %cmp
}

define i1 @or_zero(<16 x i8> %x) {
; SSE-LABEL: define i1 @or_zero(
; SSE-SAME: <16 x i8> [[X:%.*]]) #[[ATTR1]] {
; SSE-NEXT:    [[TMP1:%.*]] = icmp eq <16 x i8> [[X]], zeroinitializer
; SSE-NEXT:    [[CMP:%.*]] = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> [[TMP1]])
; SSE-NEXT:    ret i1 [[CMP]]
;
; AVX2-LABEL: define i1 @or_zero(
; AVX2-SAME: <16 x i8> [[X:%.*]]) #[[ATTR1]] {
; AVX2-NEXT:    [[TMP1:%.*]] = icmp eq <16 x i8> [[X]], zeroinitializer
; AVX2-NEXT:    [[CMP:%.*]] = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> [[TMP1]])
; AVX2-NEXT:    ret i1 [[CMP]]
;
; AVX512-LABEL: define i1 @or_zero(
; AVX512-SAME: <16 x i8> [[X:%.*]]) #[[ATTR1]] {
; AVX512-NEXT:    [[REDUCTION:%.*]] = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> [[X]])
; AVX512-NEXT:    [[CMP:%.*]] = icmp eq i8 [[REDUCTION]], 0
; AVX512-NEXT:    ret i1 [[CMP]]
;
  %reduction = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> %x)
  %cmp = icmp eq i8 %reduction, 0
  ret i1 %cmp
}

define i1 @umax_nonzero(<16 x i8> %x) {
; SSE-LABEL: define i1 @umax_nonzero(
; SSE-SAME: <16 x i8> [[X:%.*]]) #[[ATTR1]] {
; SSE-NEXT:    [[TMP1:%.*]] = icmp ne <16 x i8> [[X]], zeroinitializer
; SSE-NEXT:    [[CMP:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP1]])
; SSE-NEXT:    ret i1 [[CMP]]
;
; AVX2-LABEL: define i1 @umax_nonzero(
; AVX2-SAME: <16 x i8> [[X:%.*]]) #[[ATTR1]] {
; AVX2-NEXT:    [[TMP1:%.*]] = icmp ne <16 x i8> [[X]], zeroinitializer
; AVX2-NEXT:    [[CMP:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP1]])
; AVX2-NEXT:    ret i1 [[CMP]]
;
; AVX512-LABEL: define i1 @umax_nonzero(
; AVX512-SAME: <16 x i8> [[X:%.*]]) #[[ATTR1]] {
; AVX512-NEXT:    [[REDUCTION:%.*]] = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> [[X]])
; AVX512-NEXT:    [[CMP:%.*]] = icmp ne i8 [[REDUCTION]], 0
; AVX512-NEXT:    ret i1 [[CMP]]
;
  %reduction = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %x)
  %cmp = icmp ne i8 %reduction, 0
  ret i1 %cmp
}

define i1 @umax_zero_commuted(<16 x i8> %x) {
; SSE-LABEL: define i1 @umax_zero_commuted(
; SSE-SAME: <16 x i8> [[X:%.*]]) #[[ATTR1]] {
; SSE-NEXT:    [[TMP1:%.*]] = icmp eq <16 x i8> [[X]], zeroinitializer
; SSE-NEXT:    [[CMP:%.*]] = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> [[TMP1]])
; SSE-NEXT:    ret i1 [[CMP]]
;
; AVX2-LABEL: define i1 @umax_zero_commuted(
; AVX2-SAME: <16 x i8> [[X:%.*]]) #[[ATTR1]] {
; AVX2-NEXT:    [[TMP1:%.*]] = icmp eq <16 x i8> [[X]], zeroinitializer
; AVX2-NEXT:    [[CMP:%.*]] = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> [[TMP1]])
; AVX2-NEXT:    ret i1 [[CMP]]
;
; AVX512-LABEL: define i1 @umax_zero_commuted(
; AVX512-SAME: <16 x i8> [[X:%.*]]) #[[ATTR1]] {
; AVX512-NEXT:    [[REDUCTION:%.*]] = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> [[X]])
; AVX512-NEXT:    [[CMP:%.*]] = icmp eq i8 0, [[REDUCTION]]
; AVX512-NEXT:    ret i1 [[CMP]]
;
  %reduction = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %x)
  %cmp = icmp eq i8 0, %reduction
  ret i1 %cmp
}

define i1 @or_nonzero_multiuse(<16 x i8> %x, ptr %out) {
; CHECK-LABEL: define i1 @or_nonzero_multiuse(
; CHECK-SAME: <16 x i8> [[X:%.*]], ptr [[OUT:%.*]]) #[[ATTR1:[0-9]+]] {
; CHECK-NEXT:    [[REDUCTION:%.*]] = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> [[X]])
; CHECK-NEXT:    store i8 [[REDUCTION]], ptr [[OUT]], align 1
; CHECK-NEXT:    [[CMP:%.*]] = icmp ne i8 [[REDUCTION]], 0
; CHECK-NEXT:    ret i1 [[CMP]]
;
  %reduction = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> %x)
  store i8 %reduction, ptr %out, align 1
  %cmp = icmp ne i8 %reduction, 0
  ret i1 %cmp
}