test/Transforms/SLPVectorizer/X86/compare-node-with-reuses.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s

define i16 @test_inc_1(i16 %tnr.coerce) {
; CHECK-LABEL: define i16 @test_inc_1(
; CHECK-SAME: i16 [[TNR_COERCE:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[CALL:%.*]] = tail call zeroext i32 @idulsf(i32 noundef zeroext 2147483647)
; CHECK-NEXT:    [[CALL15:%.*]] = tail call zeroext i32 @idulsf(i32 noundef zeroext [[CALL]])
; CHECK-NEXT:    [[CALL37:%.*]] = tail call zeroext i32 @idulsf(i32 noundef zeroext 2147483647)
; CHECK-NEXT:    [[CALL58:%.*]] = tail call zeroext i32 @idulsf(i32 noundef zeroext [[CALL37]])
; CHECK-NEXT:    [[CALL80:%.*]] = tail call zeroext i32 @idulsf(i32 noundef zeroext 2147483647)
; CHECK-NEXT:    [[CALL101:%.*]] = tail call zeroext i32 @idulsf(i32 noundef zeroext [[CALL80]])
; CHECK-NEXT:    [[CALL123:%.*]] = tail call zeroext i32 @idulsf(i32 noundef zeroext 2147483647)
; CHECK-NEXT:    [[CALL144:%.*]] = tail call zeroext i32 @idulsf(i32 noundef zeroext [[CALL123]])
; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <4 x i32> poison, i32 [[CALL]], i32 0
; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[CALL37]], i32 1
; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[CALL80]], i32 2
; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[CALL123]], i32 3
; CHECK-NEXT:    [[TMP4:%.*]] = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> [[TMP3]], <4 x i32> splat (i32 2147483647))
; CHECK-NEXT:    [[TMP5:%.*]] = and <4 x i32> [[TMP4]], splat (i32 2147483647)
; CHECK-NEXT:    [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <8 x i32> <i32 0, i32 poison, i32 1, i32 poison, i32 2, i32 poison, i32 3, i32 poison>
; CHECK-NEXT:    [[TMP7:%.*]] = insertelement <8 x i32> [[TMP6]], i32 [[CALL15]], i32 1
; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <8 x i32> [[TMP7]], i32 [[CALL58]], i32 3
; CHECK-NEXT:    [[TMP9:%.*]] = insertelement <8 x i32> [[TMP8]], i32 [[CALL101]], i32 5
; CHECK-NEXT:    [[TMP10:%.*]] = insertelement <8 x i32> [[TMP9]], i32 [[CALL144]], i32 7
; CHECK-NEXT:    [[TMP11:%.*]] = shufflevector <8 x i32> [[TMP10]], <8 x i32> poison, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT:    [[TMP12:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> poison, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT:    [[TMP13:%.*]] = shufflevector <12 x i32> [[TMP11]], <12 x i32> [[TMP12]], <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT:    [[TMP14:%.*]] = icmp ne <12 x i32> [[TMP13]], splat (i32 2147483647)
; CHECK-NEXT:    [[TMP15:%.*]] = icmp eq <12 x i32> [[TMP13]], splat (i32 2147483647)
; CHECK-NEXT:    [[TMP18:%.*]] = shufflevector <12 x i1> [[TMP14]], <12 x i1> [[TMP15]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 20, i32 2, i32 21, i32 4, i32 22, i32 6, i32 23>
; CHECK-NEXT:    [[TMP16:%.*]] = select <16 x i1> [[TMP18]], <16 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 2, i16 0, i16 2, i16 0, i16 2, i16 0, i16 2, i16 0>, <16 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 2, i16 0, i16 2, i16 0, i16 2, i16 0, i16 2>
; CHECK-NEXT:    [[TMP17:%.*]] = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> [[TMP16]])
; CHECK-NEXT:    [[OP_RDX:%.*]] = add i16 [[TMP17]], [[TNR_COERCE]]
; CHECK-NEXT:    ret i16 [[OP_RDX]]
;
entry:
  %call = tail call zeroext i32 @idulsf(i32 noundef zeroext 2147483647) #2 ; 2147483647
  %0 = tail call i32 @llvm.sadd.sat.i32(i32 %call, i32 2147483647)         ; 2147483647
  %resize1 = and i32 %0, 2147483647                                        ; 2147483647
  %.not = icmp eq i32 %resize1, 2147483647                                 ; 1
  %reass.add = select i1 %.not, i16 0, i16 2                               ; 0
  %1 = icmp ne i32 %call, 2147483647                                       ; 0
  %cond10 = zext i1 %1 to i16                                              ; 0
  %call15 = tail call zeroext i32 @idulsf(i32 noundef zeroext %call) #2    ; 2147483647
  %2 = icmp ne i32 %call15, 2147483647                                      ; 0
  %cond17 = zext i1 %2 to i16                                               ; 0
  %reass.add211 = select i1 %1, i16 2, i16 0                                ; 0
  %call37 = tail call zeroext i32 @idulsf(i32 noundef zeroext 2147483647) #2; 2147483647
  %3 = tail call i32 @llvm.sadd.sat.i32(i32 %call37, i32 2147483647)        ; 2147483647
  %resize39 = and i32 %3, 2147483647                                        ; 2147483647
  %.not213 = icmp eq i32 %resize39, 2147483647                              ; 1
  %reass.add212 = select i1 %.not213, i16 0, i16 2                          ; 0
  %4 = icmp ne i32 %call37, 2147483647                                      ; 0
  %cond53 = zext i1 %4 to i16                                               ; 0
  %call58 = tail call zeroext i32 @idulsf(i32 noundef zeroext %call37) #2   ; 2147483647
  %5 = icmp ne i32 %call58, 2147483647                                      ; 0
  %cond60 = zext i1 %5 to i16                                               ; 0
  %reass.add214 = select i1 %4, i16 2, i16 0                                ; 0
  %call80 = tail call zeroext i32 @idulsf(i32 noundef zeroext 2147483647) #2; 2147483647
  %6 = tail call i32 @llvm.sadd.sat.i32(i32 %call80, i32 2147483647)        ; 2147483647
  %resize82 = and i32 %6, 2147483647                                        ; 2147483647
  %.not216 = icmp eq i32 %resize82, 2147483647                              ; 1
  %reass.add215 = select i1 %.not216, i16 0, i16 2                          ; 0
  %7 = icmp ne i32 %call80, 2147483647                                      ; 0
  %cond96 = zext i1 %7 to i16                                               ; 0
  %call101 = tail call zeroext i32 @idulsf(i32 noundef zeroext %call80) #2  ; 2147483647
  %8 = icmp ne i32 %call101, 2147483647                                     ; 0
  %cond103 = zext i1 %8 to i16                                              ; 0
  %reass.add217 = select i1 %7, i16 2, i16 0                                 ; 0
  %call123 = tail call zeroext i32 @idulsf(i32 noundef zeroext 2147483647) #2; 2147483647
  %9 = tail call i32 @llvm.sadd.sat.i32(i32 %call123, i32 2147483647)        ; 2147483647
  %resize125 = and i32 %9, 2147483647                                        ; 2147483647
  %.not219 = icmp eq i32 %resize125, 2147483647                              ; 1
  %reass.add218 = select i1 %.not219, i16 0, i16 2                           ; 0
  %10 = icmp ne i32 %call123, 2147483647                                     ; 0
  %cond139 = zext i1 %10 to i16                                              ; 0
  %call144 = tail call zeroext i32 @idulsf(i32 noundef zeroext %call123) #2  ; 2147483647
  %11 = icmp ne i32 %call144, 2147483647                                     ; 0
  %cond146 = zext i1 %11 to i16                                              ; 0
  %reass.add220 = select i1 %10, i16 2, i16 0                                ; 0
  %add7 = add i16 %tnr.coerce, %cond10       ; 0
  %conv14 = add i16 %add7, %reass.add211     ; 0
  %add20 = add i16 %conv14, %cond17          ; 0
  %add32 = add i16 %add20, %reass.add        ; 0
  %add50 = add i16 %add32, %cond53           ; 0
  %conv57 = add i16 %add50, %reass.add214    ; 0
  %add63 = add i16 %conv57, %cond60          ; 0
  %add75 = add i16 %add63, %reass.add212     ; 0
  %add93 = add i16 %add75, %cond96           ; 0
  %conv100 = add i16 %add93, %reass.add217   ; 0
  %add106 = add i16 %conv100, %cond103       ; 0
  %add118 = add i16 %add106, %reass.add215   ; 0
  %add136 = add i16 %add118, %cond139        ; 0
  %conv143 = add i16 %add136, %reass.add220  ; 0
  %add149 = add i16 %conv143, %cond146       ; 0
  %add161 = add i16 %add149, %reass.add218   ; 0
  ret i16 %add161                            ; 0
}

declare dso_local zeroext i32 @idulsf(i32 noundef zeroext)