test/CodeGen/X86/combine-clmul.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2    | FileCheck %s --check-prefixes=CHECK,SCALAR
; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2,+pclmul | FileCheck %s --check-prefixes=CHECK,SSE-PCLMUL
; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.2,+pclmul | FileCheck %s --check-prefixes=CHECK,SSE-PCLMUL
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2,+pclmul | FileCheck %s --check-prefixes=CHECK,AVX
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2,+vpclmulqdq  | FileCheck %s --check-prefixes=CHECK,AVX
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vl,+vpclmulqdq | FileCheck %s --check-prefixes=CHECK,AVX

; Test with constant 0 - should optimize to just returning 0
define i32 @clmul_i32_zero(i32 %a) {
; CHECK-LABEL: clmul_i32_zero:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xorl %eax, %eax
; CHECK-NEXT:    retq
  %res = call i32 @llvm.clmul.i32(i32 %a, i32 0)
  ret i32 %res
}

; Test with constant 1 - should optimize to just returning %a
define i32 @clmul_i32_one(i32 %a) {
; CHECK-LABEL: clmul_i32_one:
; CHECK:       # %bb.0:
; CHECK-NEXT:    movl %edi, %eax
; CHECK-NEXT:    retq
  %res = call i32 @llvm.clmul.i32(i32 %a, i32 1)
  ret i32 %res
}

; Test with power of 2 - should become a shift
define i32 @clmul_i32_pow2(i32 %a) {
; CHECK-LABEL: clmul_i32_pow2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    movl %edi, %eax
; CHECK-NEXT:    shll $4, %eax
; CHECK-NEXT:    retq
  %res = call i32 @llvm.clmul.i32(i32 %a, i32 16)  ; 0x10 = 1 << 4
  ret i32 %res
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; AVX: {{.*}}
; SCALAR: {{.*}}
; SSE-PCLMUL: {{.*}}